diff --git a/src/run.rs b/src/run.rs
index b59cd9c..2c15100 100644
--- a/src/run.rs
+++ b/src/run.rs
@@ -117,8 +117,8 @@ impl Processor {
                 let load_res = self.load_from_address_to_register(dst, src_address);
                 assert_ok!(load_res);
             }
-            Instruction::LD16bitImmediateToRegister { value, dst } => {
-                self.registers.set_combined_register(dst, value)
+            Instruction::LD16bitImmediateToRegister { dst, value } => {
+                self.registers.set_16bit_register(dst, value);
             }
         }
 
@@ -517,12 +517,16 @@ mod tests {
         assert_eq!(0xAF, processor.registers.a);
     }
 
-    #[test_case(0x01, register::Combined::BC)]
-    #[test_case(0x11, register::Combined::DE)]
-    #[test_case(0x21, register::Combined::HL)]
-    fn test_load_16bit_immediate_to_regisetr(
+    #[test_case(0x01, register::SixteenBit::Combined(register::Combined::BC))]
+    #[test_case(0x11, register::SixteenBit::Combined(register::Combined::DE))]
+    #[test_case(0x21, register::SixteenBit::Combined(register::Combined::HL))]
+    #[test_case(
+        0x31,
+        register::SixteenBit::Single(register::SingleSixteenBit::StackPointer)
+    )]
+    fn test_load_16bit_immediate_to_register(
         opcode: u8,
-        expected_dst_register: register::Combined,
+        expected_dst_register: register::SixteenBit,
     ) {
         let mut processor = Processor::default();
         // The manual doesn't specify this is little endian, but from what I can gather
@@ -542,7 +546,7 @@ mod tests {
             0x1234,
             processor
                 .registers
-                .get_combined_register(expected_dst_register)
+                .get_16bit_register(expected_dst_register)
         );
     }
 }
diff --git a/src/run/instructions.rs b/src/run/instructions.rs
index 0c2fa6c..4f7f399 100644
--- a/src/run/instructions.rs
+++ b/src/run/instructions.rs
@@ -82,7 +82,7 @@ pub enum Instruction {
     // 3.3.2.1
     LD16bitImmediateToRegister {
         value: u16,
-        dst: register::Combined,
+        dst: register::SixteenBit,
     },
 }
 
diff --git a/src/run/parse/load16/immediate.rs b/src/run/parse/load16/immediate.rs
index f4c667b..350ad9d 100644
--- a/src/run/parse/load16/immediate.rs
+++ b/src/run/parse/load16/immediate.rs
@@ -12,15 +12,28 @@ impl OpcodeParser for Immediate16BitLoadParser {
         let opcode = parse::get_opcode_from_data(data)?;
 
         match opcode {
-            0x01 => make_load_immediate_data(register::Combined::BC, data),
-            0x11 => make_load_immediate_data(register::Combined::DE, data),
-            0x21 => make_load_immediate_data(register::Combined::HL, data),
+            0x01 => make_load_immediate_data(
+                register::SixteenBit::Combined(register::Combined::BC),
+                data,
+            ),
+            0x11 => make_load_immediate_data(
+                register::SixteenBit::Combined(register::Combined::DE),
+                data,
+            ),
+            0x21 => make_load_immediate_data(
+                register::SixteenBit::Combined(register::Combined::HL),
+                data,
+            ),
+            0x31 => make_load_immediate_data(
+                register::SixteenBit::Single(register::SingleSixteenBit::StackPointer),
+                data,
+            ),
             _ => Err(Error::UnknownOpcode(opcode)),
         }
     }
 }
 
-fn make_load_immediate_data(dst: register::Combined, data: &[u8]) -> ParseResult {
+fn make_load_immediate_data(dst: register::SixteenBit, data: &[u8]) -> ParseResult {
     let opcode = parse::get_opcode_from_data(data)?;
     let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?;