From 16c275282ef5540154ca5f42aebceabb7aa5faad Mon Sep 17 00:00:00 2001
From: Nick Krichevsky <nick@ollien.com>
Date: Sat, 15 Apr 2023 15:06:00 -0400
Subject: [PATCH] Fix some clippy lints

Back on the horse...
---
 src/cpu.rs            | 2 +-
 src/cpu/parse.rs      | 2 +-
 src/cpu/run/arith8.rs | 9 +++------
 src/cpu/run/load16.rs | 6 ++----
 4 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/cpu.rs b/src/cpu.rs
index 323fb71..803f793 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -21,7 +21,7 @@ impl Processor {
     fn run(&mut self, instruction: &RunnableInstruction) {
         let run_res = run::run_instruction(self, &instruction.instruction);
         if let Err(err) = run_res {
-            panic!("Fatal CPU error occured: {}", err)
+            panic!("Fatal CPU error occured: {err}")
         }
 
         self.num_cycles += u64::from(instruction.cycles);
diff --git a/src/cpu/parse.rs b/src/cpu/parse.rs
index 603b36b..b154121 100644
--- a/src/cpu/parse.rs
+++ b/src/cpu/parse.rs
@@ -55,5 +55,5 @@ pub fn next_instruction(data: &[u8]) -> ParseResult {
 }
 
 fn get_opcode_from_data(data: &[u8]) -> Result<u8, Error> {
-    data.get(0).copied().ok_or(Error::NoData)
+    data.first().copied().ok_or(Error::NoData)
 }
diff --git a/src/cpu/run/arith8.rs b/src/cpu/run/arith8.rs
index 2898b4c..57a42c4 100644
--- a/src/cpu/run/arith8.rs
+++ b/src/cpu/run/arith8.rs
@@ -84,21 +84,18 @@ fn set_addition_flags(processor: &mut Processor, total: u8, half_carry: bool, ca
     processor.registers.set_flag_bit(
         register::Flag::Zero,
         // carry must be false, as if it's true, the value is indeed > 0
-        if total == 0 && !carry { 1 } else { 0 },
+        (total == 0 && !carry).into(),
     );
 
-    let half_carry_bit = if half_carry { 1 } else { 0 };
-
     processor
         .registers
         .set_flag_bit(register::Flag::Subtract, 0);
 
     processor
         .registers
-        .set_flag_bit(register::Flag::HalfCarry, half_carry_bit);
+        .set_flag_bit(register::Flag::HalfCarry, half_carry.into());
 
-    let full_carry_bit = if carry { 1 } else { 0 };
     processor
         .registers
-        .set_flag_bit(register::Flag::Carry, full_carry_bit);
+        .set_flag_bit(register::Flag::Carry, carry.into());
 }
diff --git a/src/cpu/run/load16.rs b/src/cpu/run/load16.rs
index 68ced79..c7f1d01 100644
--- a/src/cpu/run/load16.rs
+++ b/src/cpu/run/load16.rs
@@ -33,14 +33,12 @@ impl InstructionRunner<SixteenBitLoadInstruction> for SixteenBitLoadRunner {
 
                 let (new_sp, half_carry, carry) = current_sp.add_with_carry(offset);
 
-                let half_carry_bit = if half_carry { 1 } else { 0 };
-                let carry_bit = if carry { 1 } else { 0 };
                 processor
                     .registers
-                    .set_flag_bit(register::Flag::Carry, carry_bit);
+                    .set_flag_bit(register::Flag::Carry, carry.into());
                 processor
                     .registers
-                    .set_flag_bit(register::Flag::HalfCarry, half_carry_bit);
+                    .set_flag_bit(register::Flag::HalfCarry, half_carry.into());
 
                 // Manual says we reset these here.
                 processor