Replace 'ld' with Load
parent
deeacd917a
commit
29ccffccf7
44
src/run.rs
44
src/run.rs
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@ -49,42 +49,42 @@ impl Processor {
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fn run_8_bit_load(&mut self, instruction: &EightBitLoadInstruction) {
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match *instruction {
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EightBitLoadInstruction::LDImmediateToRegister { value, register } => {
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EightBitLoadInstruction::LoadImmediateToRegister { value, register } => {
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self.registers.set_single_8bit_register(register, value);
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}
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EightBitLoadInstruction::LDBetweenRegisters { dst, src } => {
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EightBitLoadInstruction::LoadBetweenRegisters { dst, src } => {
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let src_value = self.registers.get_single_8bit_register(src);
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self.registers.set_single_8bit_register(dst, src_value);
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}
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EightBitLoadInstruction::LDFromRegisterAddress { src, dst } => {
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EightBitLoadInstruction::LoadFromRegisterAddress { src, dst } => {
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let load_res = self.load_from_register_address_to_register(dst, src);
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDFromImmediateAddress { src_address, dst } => {
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EightBitLoadInstruction::LoadFromImmediateAddress { src_address, dst } => {
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let load_res = self.load_from_address_to_register(dst, src_address.into());
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDToRegisterAddress { src, dst } => {
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EightBitLoadInstruction::LoadToRegisterAddress { src, dst } => {
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let load_res = self.load_from_register_to_register_address(dst, src);
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDToImmediateAddress { src, dst_address } => {
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EightBitLoadInstruction::LoadToImmediateAddress { src, dst_address } => {
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let load_res = self.load_from_register_to_address(dst_address.into(), src);
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDnToHLAddress { value } => {
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EightBitLoadInstruction::LoadnToHLAddress { value } => {
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let dest_address = self.registers.get_combined_register(register::Combined::HL);
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let load_res = self.load_8bit_immediate_to_address(dest_address.into(), value);
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStart {
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EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStart {
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offset_register,
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dst,
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} => {
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@ -95,7 +95,7 @@ impl Processor {
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStart {
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EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStart {
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src,
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offset_register,
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} => {
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@ -106,7 +106,7 @@ impl Processor {
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDFromRegisterAddressThenDec { dst, src } => {
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EightBitLoadInstruction::LoadFromRegisterAddressThenDec { dst, src } => {
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let load_res = self.load_from_register_address_to_register(dst, src);
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assert_ok!(load_res);
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@ -114,7 +114,7 @@ impl Processor {
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self.registers.set_combined_register(src, src_address - 1);
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}
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EightBitLoadInstruction::LDFromRegisterAddressThenInc { dst, src } => {
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EightBitLoadInstruction::LoadFromRegisterAddressThenInc { dst, src } => {
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let load_res = self.load_from_register_address_to_register(dst, src);
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assert_ok!(load_res);
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@ -122,7 +122,7 @@ impl Processor {
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self.registers.set_combined_register(src, src_address + 1);
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}
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EightBitLoadInstruction::LDToRegisterAddressThenDec { dst, src } => {
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EightBitLoadInstruction::LoadToRegisterAddressThenDec { dst, src } => {
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let dst_address = self.registers.get_combined_register(dst);
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let load_res = self.load_from_register_to_address(dst_address.into(), src);
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assert_ok!(load_res);
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@ -130,7 +130,7 @@ impl Processor {
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self.registers.set_combined_register(dst, dst_address - 1);
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}
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EightBitLoadInstruction::LDToRegisterAddressThenInc { dst, src } => {
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EightBitLoadInstruction::LoadToRegisterAddressThenInc { dst, src } => {
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let dst_address = self.registers.get_combined_register(dst);
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let load_res = self.load_from_register_to_address(dst_address.into(), src);
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assert_ok!(load_res);
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@ -138,7 +138,7 @@ impl Processor {
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self.registers.set_combined_register(dst, dst_address + 1);
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}
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EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStartByImmediate {
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EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStartByImmediate {
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src,
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offset,
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} => {
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@ -147,7 +147,7 @@ impl Processor {
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assert_ok!(load_res);
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}
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EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStartByImmediate {
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EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStartByImmediate {
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dst,
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offset,
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} => {
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@ -160,16 +160,16 @@ impl Processor {
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fn run_16_bit_load(&mut self, instruction: &SixteenBitLoadInstruction) {
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match *instruction {
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SixteenBitLoadInstruction::LDImmediateToRegister { dst, value } => {
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SixteenBitLoadInstruction::LoadImmediateToRegister { dst, value } => {
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self.registers.set_16bit_register(dst, value);
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}
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SixteenBitLoadInstruction::LDBetweenRegisters { dst, src } => {
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SixteenBitLoadInstruction::LoadBetweenRegisters { dst, src } => {
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let value = self.registers.get_16bit_register(src);
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self.registers.set_16bit_register(dst, value);
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}
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SixteenBitLoadInstruction::LDEffectiveAddress { dst, offset } => {
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SixteenBitLoadInstruction::LoadEffectiveAddress { dst, offset } => {
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let current_sp = self
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.registers
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.get_single_16bit_register(register::SingleSixteenBit::StackPointer);
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@ -355,9 +355,9 @@ mod tests {
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#[test_case(0x1E, register::SingleEightBit::E)]
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#[test_case(0x26, register::SingleEightBit::H)]
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#[test_case(0x2E, register::SingleEightBit::L)]
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fn test_load_immediate(ld_opcode: u8, expected_register: register::SingleEightBit) {
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fn test_load_immediate(load_opcode: u8, expected_register: register::SingleEightBit) {
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let mut processor = Processor::default();
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let data = [ld_opcode, 0x23, 0x00, 0x01];
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let data = [load_opcode, 0x23, 0x00, 0x01];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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@ -425,7 +425,7 @@ mod tests {
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#[test_case(0x67, register::SingleEightBit::H, register::SingleEightBit::A)]
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#[test_case(0x6F, register::SingleEightBit::L, register::SingleEightBit::A)]
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fn test_load_register(
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ld_opcode: u8,
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load_opcode: u8,
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dst_register: register::SingleEightBit,
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src_register: register::SingleEightBit,
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) {
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@ -434,7 +434,7 @@ mod tests {
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.registers
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.set_single_8bit_register(src_register, 0x45);
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let data = [ld_opcode, 0x00];
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let data = [load_opcode, 0x00];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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@ -5,17 +5,17 @@ use crate::register;
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#[derive(Debug, Clone)]
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pub enum SixteenBitLoadInstruction {
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// 3.3.2.1
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LDImmediateToRegister {
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LoadImmediateToRegister {
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value: u16,
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dst: register::SixteenBit,
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},
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// 3.3.2.2
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LDBetweenRegisters {
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LoadBetweenRegisters {
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dst: register::SixteenBit,
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src: register::SixteenBit,
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},
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// 3.3.3.4
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LDEffectiveAddress {
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LoadEffectiveAddress {
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dst: register::Combined,
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offset: i8,
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},
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@ -5,89 +5,89 @@ use crate::register;
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#[derive(Debug, Clone)]
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pub enum EightBitLoadInstruction {
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// 3.3.1.1
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LDImmediateToRegister {
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LoadImmediateToRegister {
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value: u8,
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register: register::SingleEightBit,
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},
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// 3.3.1.2, excluding the (hl) instructions, 3.3.1.3, excluding the (nn) instructions
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// and 3.3.1.4 excluding the (nn) instructions
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LDBetweenRegisters {
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LoadBetweenRegisters {
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dst: register::SingleEightBit,
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src: register::SingleEightBit,
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},
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// 3.3.1.2/3.3.1.3, only the loading from (nn) instructions
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LDFromRegisterAddress {
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LoadFromRegisterAddress {
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// src, unlike some of the other instructions, is a 16bit combined register that will be
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// dereferenced to get the value to place into the dst register
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src: register::Combined,
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dst: register::SingleEightBit,
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},
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// 3.3.1.5 - load to register relative to $FF00 (the address of the i/o registers)
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LDFromMemoryRelativeToIORegisterStart {
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LoadFromMemoryRelativeToIORegisterStart {
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// A register whose value will be used to get the address relative to FF00
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offset_register: register::SingleEightBit,
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dst: register::SingleEightBit,
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},
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// 3.3.1.6 - load to memory relative to $FF00 (the address of the i/o registers)
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LDToMemoryRelativeToIORegisterStart {
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LoadToMemoryRelativeToIORegisterStart {
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src: register::SingleEightBit,
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// A register whose value will be used to get the address relative to FF00
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offset_register: register::SingleEightBit,
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},
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// 3.3.1.20
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LDFromMemoryRelativeToIORegisterStartByImmediate {
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LoadFromMemoryRelativeToIORegisterStartByImmediate {
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dst: register::SingleEightBit,
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offset: u8,
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},
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// 3.3.1.19
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LDToMemoryRelativeToIORegisterStartByImmediate {
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LoadToMemoryRelativeToIORegisterStartByImmediate {
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offset: u8,
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src: register::SingleEightBit,
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},
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LDFromImmediateAddress {
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LoadFromImmediateAddress {
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src_address: u16,
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dst: register::SingleEightBit,
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},
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// 3.3.1.2, only the loading to (hl) instructions
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// 3.3.1.4, only the loading to (nn) instructions
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LDToRegisterAddress {
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LoadToRegisterAddress {
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src: register::SingleEightBit,
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// dst, unlike some other instructions, is a 16bit combined register that holds
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// the address we will write the value to
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dst: register::Combined,
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},
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// 3.3.1.4, only the loading to (nn) immediate instrution
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LDToImmediateAddress {
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LoadToImmediateAddress {
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src: register::SingleEightBit,
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dst_address: u16,
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},
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// 3.3.1.2, but the (hl), n instruction [why is this in this section? it's so out of place]
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LDnToHLAddress {
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LoadnToHLAddress {
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value: u8,
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},
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// 3.3.1.{7,8,9}
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LDFromRegisterAddressThenDec {
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LoadFromRegisterAddressThenDec {
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// The src, unlike some other destination instructions, refers to a register
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// whose address will be dereferenced (and then decremented after the load)
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src: register::Combined,
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dst: register::SingleEightBit,
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},
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// 3.3.1.{13,14,15}
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LDFromRegisterAddressThenInc {
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LoadFromRegisterAddressThenInc {
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// The src, unlike some other destination instructions, refers to a register
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// whose address will be dereferenced (and then incremented after the load)
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src: register::Combined,
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dst: register::SingleEightBit,
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},
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// 3.3.1.{10,11,12}
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LDToRegisterAddressThenDec {
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LoadToRegisterAddressThenDec {
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src: register::SingleEightBit,
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// The destination, unlike some other destination instructions, refers to a register
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// whose address will be dereferenced (and then decremented after the load)
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dst: register::Combined,
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},
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// 3.3.1.{16,17,18}
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LDToRegisterAddressThenInc {
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LoadToRegisterAddressThenInc {
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src: register::SingleEightBit,
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// The destination, unlike some other destination instructions, refers to a register
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// whose address will be dereferenced (and then incremented after the load)
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@ -45,7 +45,7 @@ fn make_load_immediate_data(dst: register::SixteenBit, data: &[u8]) -> ParseResu
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Ok((
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RunnableInstruction {
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instruction: Instruction::SixteenBitLoad(
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SixteenBitLoadInstruction::LDImmediateToRegister { value, dst },
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SixteenBitLoadInstruction::LoadImmediateToRegister { value, dst },
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),
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cycles: 12,
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},
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@ -75,7 +75,7 @@ fn make_load_effective_address(dst: register::Combined, data: &[u8]) -> ParseRes
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Ok((
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RunnableInstruction {
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instruction: Instruction::SixteenBitLoad(
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SixteenBitLoadInstruction::LDEffectiveAddress {
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SixteenBitLoadInstruction::LoadEffectiveAddress {
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dst,
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offset: signed_value,
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},
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@ -13,7 +13,7 @@ impl OpcodeParser for Between16BitRegisterParser {
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fn parse_opcode(data: &[u8]) -> ParseResult {
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let opcode = parse::get_opcode_from_data(data)?;
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match opcode {
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0xF9 => make_ld_between_register_data(
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0xF9 => make_load_between_register_data(
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register::SixteenBit::Single(register::SingleSixteenBit::StackPointer),
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register::SixteenBit::Combined(register::Combined::HL),
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data,
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@ -23,7 +23,7 @@ impl OpcodeParser for Between16BitRegisterParser {
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}
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}
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fn make_ld_between_register_data(
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fn make_load_between_register_data(
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dst: register::SixteenBit,
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src: register::SixteenBit,
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data: &[u8],
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@ -33,7 +33,7 @@ fn make_ld_between_register_data(
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(
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RunnableInstruction {
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instruction: Instruction::SixteenBitLoad(
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SixteenBitLoadInstruction::LDBetweenRegisters { dst, src },
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SixteenBitLoadInstruction::LoadBetweenRegisters { dst, src },
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),
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cycles: 4,
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},
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@ -36,7 +36,7 @@ fn make_load_immediate_data(register: register::SingleEightBit, data: &[u8]) ->
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Ok((
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RunnableInstruction {
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instruction: Instruction::EightBitLoad(
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EightBitLoadInstruction::LDImmediateToRegister {
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EightBitLoadInstruction::LoadImmediateToRegister {
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register,
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value: *value,
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},
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@ -34,31 +34,31 @@ fn parse_load_from_register_to_address(data: &[u8]) -> ParseResult {
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let opcode = parse::get_opcode_from_data(data)?;
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match opcode {
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0x02 => {
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make_ld_to_register_address(register::Combined::BC, register::SingleEightBit::A, data)
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make_load_to_register_address(register::Combined::BC, register::SingleEightBit::A, data)
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}
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0x12 => {
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make_ld_to_register_address(register::Combined::DE, register::SingleEightBit::A, data)
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make_load_to_register_address(register::Combined::DE, register::SingleEightBit::A, data)
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}
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0x70 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::B, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::B, data)
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}
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0x71 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::C, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::C, data)
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}
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0x72 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::D, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::D, data)
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}
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0x73 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::E, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::E, data)
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}
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0x74 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::H, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::H, data)
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}
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0x75 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::L, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::L, data)
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}
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0x77 => {
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make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::A, data)
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make_load_to_register_address(register::Combined::HL, register::SingleEightBit::A, data)
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}
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_ => Err(Error::UnknownOpcode(opcode)),
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}
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@ -67,49 +67,67 @@ fn parse_load_from_register_to_address(data: &[u8]) -> ParseResult {
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fn parse_load_from_address_to_register(data: &[u8]) -> ParseResult {
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let opcode = parse::get_opcode_from_data(data)?;
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match opcode {
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0x0A => {
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make_ld_from_register_address(register::SingleEightBit::A, register::Combined::BC, data)
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}
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0x1A => {
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make_ld_from_register_address(register::SingleEightBit::A, register::Combined::DE, data)
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}
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0x46 => {
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make_ld_from_register_address(register::SingleEightBit::B, register::Combined::HL, data)
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}
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0x4E => {
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make_ld_from_register_address(register::SingleEightBit::C, register::Combined::HL, data)
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}
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0x56 => {
|
||||
make_ld_from_register_address(register::SingleEightBit::D, register::Combined::HL, data)
|
||||
}
|
||||
0x5E => {
|
||||
make_ld_from_register_address(register::SingleEightBit::E, register::Combined::HL, data)
|
||||
}
|
||||
0x66 => {
|
||||
make_ld_from_register_address(register::SingleEightBit::H, register::Combined::HL, data)
|
||||
}
|
||||
0x6E => {
|
||||
make_ld_from_register_address(register::SingleEightBit::L, register::Combined::HL, data)
|
||||
}
|
||||
0x7E => {
|
||||
make_ld_from_register_address(register::SingleEightBit::A, register::Combined::HL, data)
|
||||
}
|
||||
0x0A => make_load_from_register_address(
|
||||
register::SingleEightBit::A,
|
||||
register::Combined::BC,
|
||||
data,
|
||||
),
|
||||
0x1A => make_load_from_register_address(
|
||||
register::SingleEightBit::A,
|
||||
register::Combined::DE,
|
||||
data,
|
||||
),
|
||||
0x46 => make_load_from_register_address(
|
||||
register::SingleEightBit::B,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
0x4E => make_load_from_register_address(
|
||||
register::SingleEightBit::C,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
0x56 => make_load_from_register_address(
|
||||
register::SingleEightBit::D,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
0x5E => make_load_from_register_address(
|
||||
register::SingleEightBit::E,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
0x66 => make_load_from_register_address(
|
||||
register::SingleEightBit::H,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
0x6E => make_load_from_register_address(
|
||||
register::SingleEightBit::L,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
0x7E => make_load_from_register_address(
|
||||
register::SingleEightBit::A,
|
||||
register::Combined::HL,
|
||||
data,
|
||||
),
|
||||
|
||||
0xF2 => make_ld_from_memory_relative_to_io_register_start(
|
||||
0xF2 => make_load_from_memory_relative_to_io_register_start(
|
||||
register::SingleEightBit::C,
|
||||
register::SingleEightBit::A,
|
||||
data,
|
||||
),
|
||||
0xE2 => make_ld_to_memory_relative_to_io_register_start(
|
||||
0xE2 => make_load_to_memory_relative_to_io_register_start(
|
||||
register::SingleEightBit::C,
|
||||
register::SingleEightBit::A,
|
||||
data,
|
||||
),
|
||||
0xF0 => make_ld_from_memory_relative_to_io_register_start_by_immediate(
|
||||
0xF0 => make_load_from_memory_relative_to_io_register_start_by_immediate(
|
||||
register::SingleEightBit::A,
|
||||
data,
|
||||
),
|
||||
0xE0 => make_ld_to_memory_relative_to_io_register_start_by_immediate(
|
||||
0xE0 => make_load_to_memory_relative_to_io_register_start_by_immediate(
|
||||
register::SingleEightBit::A,
|
||||
data,
|
||||
),
|
||||
|
|
@ -121,9 +139,9 @@ fn parse_load_from_address_to_register(data: &[u8]) -> ParseResult {
|
|||
fn parse_load_immediate_instructions(data: &[u8]) -> ParseResult {
|
||||
let opcode = parse::get_opcode_from_data(data)?;
|
||||
match opcode {
|
||||
0x36 => make_ld_n_to_hl_address(data),
|
||||
0xFA => make_ld_from_immediate_address(register::SingleEightBit::A, data),
|
||||
0xEA => make_ld_to_immediate_address(register::SingleEightBit::A, data),
|
||||
0x36 => make_load_n_to_hl_address(data),
|
||||
0xFA => make_load_from_immediate_address(register::SingleEightBit::A, data),
|
||||
0xEA => make_load_to_immediate_address(register::SingleEightBit::A, data),
|
||||
_ => Err(Error::UnknownOpcode(opcode)),
|
||||
}
|
||||
}
|
||||
|
|
@ -131,35 +149,35 @@ fn parse_load_immediate_instructions(data: &[u8]) -> ParseResult {
|
|||
fn parse_load_from_register_to_address_and_do_arithmetic(data: &[u8]) -> ParseResult {
|
||||
let opcode = parse::get_opcode_from_data(data)?;
|
||||
match opcode {
|
||||
0x32 => make_ld_to_address_and_do_arithmetic(
|
||||
0x32 => make_load_to_address_and_do_arithmetic(
|
||||
register::Combined::HL,
|
||||
register::SingleEightBit::A,
|
||||
|dst, src| EightBitLoadInstruction::LDToRegisterAddressThenDec { dst, src },
|
||||
|dst, src| EightBitLoadInstruction::LoadToRegisterAddressThenDec { dst, src },
|
||||
data,
|
||||
),
|
||||
0x22 => make_ld_to_address_and_do_arithmetic(
|
||||
0x22 => make_load_to_address_and_do_arithmetic(
|
||||
register::Combined::HL,
|
||||
register::SingleEightBit::A,
|
||||
|dst, src| EightBitLoadInstruction::LDToRegisterAddressThenInc { dst, src },
|
||||
|dst, src| EightBitLoadInstruction::LoadToRegisterAddressThenInc { dst, src },
|
||||
data,
|
||||
),
|
||||
0x3A => make_ld_from_address_and_do_arithmetic(
|
||||
0x3A => make_load_from_address_and_do_arithmetic(
|
||||
register::SingleEightBit::A,
|
||||
register::Combined::HL,
|
||||
|dst, src| EightBitLoadInstruction::LDFromRegisterAddressThenDec { dst, src },
|
||||
|dst, src| EightBitLoadInstruction::LoadFromRegisterAddressThenDec { dst, src },
|
||||
data,
|
||||
),
|
||||
0x2A => make_ld_from_address_and_do_arithmetic(
|
||||
0x2A => make_load_from_address_and_do_arithmetic(
|
||||
register::SingleEightBit::A,
|
||||
register::Combined::HL,
|
||||
|dst, src| EightBitLoadInstruction::LDFromRegisterAddressThenInc { dst, src },
|
||||
|dst, src| EightBitLoadInstruction::LoadFromRegisterAddressThenInc { dst, src },
|
||||
data,
|
||||
),
|
||||
_ => Err(Error::UnknownOpcode(opcode)),
|
||||
}
|
||||
}
|
||||
|
||||
fn make_ld_from_register_address(
|
||||
fn make_load_from_register_address(
|
||||
dst: register::SingleEightBit,
|
||||
src: register::Combined,
|
||||
data: &[u8],
|
||||
|
|
@ -169,7 +187,7 @@ fn make_ld_from_register_address(
|
|||
(
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDFromRegisterAddress { src, dst },
|
||||
EightBitLoadInstruction::LoadFromRegisterAddress { src, dst },
|
||||
),
|
||||
cycles: 8,
|
||||
},
|
||||
|
|
@ -179,7 +197,7 @@ fn make_ld_from_register_address(
|
|||
.ok_or(Error::NoData)
|
||||
}
|
||||
|
||||
fn make_ld_to_register_address(
|
||||
fn make_load_to_register_address(
|
||||
dst: register::Combined,
|
||||
src: register::SingleEightBit,
|
||||
data: &[u8],
|
||||
|
|
@ -189,7 +207,7 @@ fn make_ld_to_register_address(
|
|||
(
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDToRegisterAddress { src, dst },
|
||||
EightBitLoadInstruction::LoadToRegisterAddress { src, dst },
|
||||
),
|
||||
cycles: 8,
|
||||
},
|
||||
|
|
@ -199,7 +217,7 @@ fn make_ld_to_register_address(
|
|||
.ok_or(Error::NoData)
|
||||
}
|
||||
|
||||
fn make_ld_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) -> ParseResult {
|
||||
fn make_load_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) -> ParseResult {
|
||||
let opcode = parse::get_opcode_from_data(data)?;
|
||||
let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?;
|
||||
|
||||
|
|
@ -208,7 +226,7 @@ fn make_ld_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) ->
|
|||
Ok((
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDFromImmediateAddress { src_address, dst },
|
||||
EightBitLoadInstruction::LoadFromImmediateAddress { src_address, dst },
|
||||
),
|
||||
cycles: 16,
|
||||
},
|
||||
|
|
@ -217,7 +235,7 @@ fn make_ld_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) ->
|
|||
))
|
||||
}
|
||||
|
||||
fn make_ld_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> ParseResult {
|
||||
fn make_load_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> ParseResult {
|
||||
let opcode = parse::get_opcode_from_data(data)?;
|
||||
let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?;
|
||||
|
||||
|
|
@ -225,10 +243,9 @@ fn make_ld_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> P
|
|||
let dst_address = u16::from_le_bytes([args[0], args[1]]);
|
||||
Ok((
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(EightBitLoadInstruction::LDToImmediateAddress {
|
||||
src,
|
||||
dst_address,
|
||||
}),
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LoadToImmediateAddress { src, dst_address },
|
||||
),
|
||||
cycles: 16,
|
||||
},
|
||||
// This can't fail if get(1..=2) passed
|
||||
|
|
@ -236,12 +253,12 @@ fn make_ld_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> P
|
|||
))
|
||||
}
|
||||
|
||||
fn make_ld_n_to_hl_address(data: &[u8]) -> ParseResult {
|
||||
fn make_load_n_to_hl_address(data: &[u8]) -> ParseResult {
|
||||
let opcode = parse::get_opcode_from_data(data)?;
|
||||
let value = data.get(1).ok_or(Error::NotEnoughArgs(opcode))?;
|
||||
Ok((
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(EightBitLoadInstruction::LDnToHLAddress {
|
||||
instruction: Instruction::EightBitLoad(EightBitLoadInstruction::LoadnToHLAddress {
|
||||
value: *value,
|
||||
}),
|
||||
cycles: 12,
|
||||
|
|
@ -251,7 +268,7 @@ fn make_ld_n_to_hl_address(data: &[u8]) -> ParseResult {
|
|||
))
|
||||
}
|
||||
|
||||
fn make_ld_from_memory_relative_to_io_register_start(
|
||||
fn make_load_from_memory_relative_to_io_register_start(
|
||||
offset_register: register::SingleEightBit,
|
||||
dst: register::SingleEightBit,
|
||||
data: &[u8],
|
||||
|
|
@ -261,7 +278,7 @@ fn make_ld_from_memory_relative_to_io_register_start(
|
|||
(
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStart {
|
||||
EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStart {
|
||||
offset_register,
|
||||
dst,
|
||||
},
|
||||
|
|
@ -275,7 +292,7 @@ fn make_ld_from_memory_relative_to_io_register_start(
|
|||
.ok_or(Error::NoData)
|
||||
}
|
||||
|
||||
fn make_ld_to_memory_relative_to_io_register_start(
|
||||
fn make_load_to_memory_relative_to_io_register_start(
|
||||
offset_register: register::SingleEightBit,
|
||||
src: register::SingleEightBit,
|
||||
data: &[u8],
|
||||
|
|
@ -285,7 +302,7 @@ fn make_ld_to_memory_relative_to_io_register_start(
|
|||
(
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStart {
|
||||
EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStart {
|
||||
src,
|
||||
offset_register,
|
||||
},
|
||||
|
|
@ -299,7 +316,7 @@ fn make_ld_to_memory_relative_to_io_register_start(
|
|||
.ok_or(Error::NoData)
|
||||
}
|
||||
|
||||
fn make_ld_to_memory_relative_to_io_register_start_by_immediate(
|
||||
fn make_load_to_memory_relative_to_io_register_start_by_immediate(
|
||||
src: register::SingleEightBit,
|
||||
data: &[u8],
|
||||
) -> ParseResult {
|
||||
|
|
@ -309,7 +326,7 @@ fn make_ld_to_memory_relative_to_io_register_start_by_immediate(
|
|||
Ok((
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStartByImmediate {
|
||||
EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStartByImmediate {
|
||||
src,
|
||||
offset: *value,
|
||||
},
|
||||
|
|
@ -321,7 +338,7 @@ fn make_ld_to_memory_relative_to_io_register_start_by_immediate(
|
|||
))
|
||||
}
|
||||
|
||||
fn make_ld_from_memory_relative_to_io_register_start_by_immediate(
|
||||
fn make_load_from_memory_relative_to_io_register_start_by_immediate(
|
||||
dst: register::SingleEightBit,
|
||||
data: &[u8],
|
||||
) -> ParseResult {
|
||||
|
|
@ -331,7 +348,7 @@ fn make_ld_from_memory_relative_to_io_register_start_by_immediate(
|
|||
Ok((
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStartByImmediate {
|
||||
EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStartByImmediate {
|
||||
offset: *value,
|
||||
dst,
|
||||
},
|
||||
|
|
@ -343,9 +360,9 @@ fn make_ld_from_memory_relative_to_io_register_start_by_immediate(
|
|||
))
|
||||
}
|
||||
|
||||
/// `make_ld_to_address_and_do_arithmetic` will make one of the instructions that load to memory and either increment
|
||||
/// `make_load_to_address_and_do_arithmetic` will make one of the instructions that load to memory and either increment
|
||||
/// or decerement. The instruction itself will be produced by the given `make` function.
|
||||
fn make_ld_to_address_and_do_arithmetic<
|
||||
fn make_load_to_address_and_do_arithmetic<
|
||||
F: Fn(register::Combined, register::SingleEightBit) -> EightBitLoadInstruction,
|
||||
>(
|
||||
dst: register::Combined,
|
||||
|
|
@ -356,9 +373,9 @@ fn make_ld_to_address_and_do_arithmetic<
|
|||
make_load_and_do_arithmetic(|| make(dst, src), data)
|
||||
}
|
||||
|
||||
/// `make_ld_to_address_and_do_arithmetic` will make one of the instructions that load from memory and either increment
|
||||
/// `make_load_to_address_and_do_arithmetic` will make one of the instructions that load from memory and either increment
|
||||
/// or decerement. The instruction itself will be produced by the given `make` function.
|
||||
fn make_ld_from_address_and_do_arithmetic<
|
||||
fn make_load_from_address_and_do_arithmetic<
|
||||
F: Fn(register::SingleEightBit, register::Combined) -> EightBitLoadInstruction,
|
||||
>(
|
||||
dst: register::SingleEightBit,
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ fn make_load_between_register_data(
|
|||
(
|
||||
RunnableInstruction {
|
||||
instruction: Instruction::EightBitLoad(
|
||||
EightBitLoadInstruction::LDBetweenRegisters { dst, src },
|
||||
EightBitLoadInstruction::LoadBetweenRegisters { dst, src },
|
||||
),
|
||||
cycles: 4,
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue