ollien
/
ferris-boi
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Replace 'ld' with Load

jsmoo
Nick Krichevsky 2022-04-14 21:30:49 -04:00
parent deeacd917a
commit 29ccffccf7
8 changed files with 140 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
src/run.rs
View File

@ -49,42 +49,42 @@ impl Processor {
fn run_8_bit_load(&mut self, instruction: &EightBitLoadInstruction) { fn run_8_bit_load(&mut self, instruction: &EightBitLoadInstruction) {
match *instruction { match *instruction {
EightBitLoadInstruction::LDImmediateToRegister { value, register } => { EightBitLoadInstruction::LoadImmediateToRegister { value, register } => {
self.registers.set_single_8bit_register(register, value); self.registers.set_single_8bit_register(register, value);
} }
EightBitLoadInstruction::LDBetweenRegisters { dst, src } => { EightBitLoadInstruction::LoadBetweenRegisters { dst, src } => {
let src_value = self.registers.get_single_8bit_register(src); let src_value = self.registers.get_single_8bit_register(src);
self.registers.set_single_8bit_register(dst, src_value); self.registers.set_single_8bit_register(dst, src_value);
} }
EightBitLoadInstruction::LDFromRegisterAddress { src, dst } => { EightBitLoadInstruction::LoadFromRegisterAddress { src, dst } => {
let load_res = self.load_from_register_address_to_register(dst, src); let load_res = self.load_from_register_address_to_register(dst, src);
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDFromImmediateAddress { src_address, dst } => { EightBitLoadInstruction::LoadFromImmediateAddress { src_address, dst } => {
let load_res = self.load_from_address_to_register(dst, src_address.into()); let load_res = self.load_from_address_to_register(dst, src_address.into());
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDToRegisterAddress { src, dst } => { EightBitLoadInstruction::LoadToRegisterAddress { src, dst } => {
let load_res = self.load_from_register_to_register_address(dst, src); let load_res = self.load_from_register_to_register_address(dst, src);
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDToImmediateAddress { src, dst_address } => { EightBitLoadInstruction::LoadToImmediateAddress { src, dst_address } => {
let load_res = self.load_from_register_to_address(dst_address.into(), src); let load_res = self.load_from_register_to_address(dst_address.into(), src);
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDnToHLAddress { value } => { EightBitLoadInstruction::LoadnToHLAddress { value } => {
let dest_address = self.registers.get_combined_register(register::Combined::HL); let dest_address = self.registers.get_combined_register(register::Combined::HL);
let load_res = self.load_8bit_immediate_to_address(dest_address.into(), value); let load_res = self.load_8bit_immediate_to_address(dest_address.into(), value);
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStart { EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStart {
offset_register, offset_register,
dst, dst,
} => { } => {
@ -95,7 +95,7 @@ impl Processor {
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStart { EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStart {
src, src,
offset_register, offset_register,
} => { } => {
@ -106,7 +106,7 @@ impl Processor {
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDFromRegisterAddressThenDec { dst, src } => { EightBitLoadInstruction::LoadFromRegisterAddressThenDec { dst, src } => {
let load_res = self.load_from_register_address_to_register(dst, src); let load_res = self.load_from_register_address_to_register(dst, src);
assert_ok!(load_res); assert_ok!(load_res);
@ -114,7 +114,7 @@ impl Processor {
self.registers.set_combined_register(src, src_address - 1); self.registers.set_combined_register(src, src_address - 1);
} }
EightBitLoadInstruction::LDFromRegisterAddressThenInc { dst, src } => { EightBitLoadInstruction::LoadFromRegisterAddressThenInc { dst, src } => {
let load_res = self.load_from_register_address_to_register(dst, src); let load_res = self.load_from_register_address_to_register(dst, src);
assert_ok!(load_res); assert_ok!(load_res);
@ -122,7 +122,7 @@ impl Processor {
self.registers.set_combined_register(src, src_address + 1); self.registers.set_combined_register(src, src_address + 1);
} }
EightBitLoadInstruction::LDToRegisterAddressThenDec { dst, src } => { EightBitLoadInstruction::LoadToRegisterAddressThenDec { dst, src } => {
let dst_address = self.registers.get_combined_register(dst); let dst_address = self.registers.get_combined_register(dst);
let load_res = self.load_from_register_to_address(dst_address.into(), src); let load_res = self.load_from_register_to_address(dst_address.into(), src);
assert_ok!(load_res); assert_ok!(load_res);
@ -130,7 +130,7 @@ impl Processor {
self.registers.set_combined_register(dst, dst_address - 1); self.registers.set_combined_register(dst, dst_address - 1);
} }
EightBitLoadInstruction::LDToRegisterAddressThenInc { dst, src } => { EightBitLoadInstruction::LoadToRegisterAddressThenInc { dst, src } => {
let dst_address = self.registers.get_combined_register(dst); let dst_address = self.registers.get_combined_register(dst);
let load_res = self.load_from_register_to_address(dst_address.into(), src); let load_res = self.load_from_register_to_address(dst_address.into(), src);
assert_ok!(load_res); assert_ok!(load_res);
@ -138,7 +138,7 @@ impl Processor {
self.registers.set_combined_register(dst, dst_address + 1); self.registers.set_combined_register(dst, dst_address + 1);
} }
EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStartByImmediate { EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStartByImmediate {
src, src,
offset, offset,
} => { } => {
@ -147,7 +147,7 @@ impl Processor {
assert_ok!(load_res); assert_ok!(load_res);
} }
EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStartByImmediate { EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStartByImmediate {
dst, dst,
offset, offset,
} => { } => {
@ -160,16 +160,16 @@ impl Processor {
fn run_16_bit_load(&mut self, instruction: &SixteenBitLoadInstruction) { fn run_16_bit_load(&mut self, instruction: &SixteenBitLoadInstruction) {
match *instruction { match *instruction {
SixteenBitLoadInstruction::LDImmediateToRegister { dst, value } => { SixteenBitLoadInstruction::LoadImmediateToRegister { dst, value } => {
self.registers.set_16bit_register(dst, value); self.registers.set_16bit_register(dst, value);
} }
SixteenBitLoadInstruction::LDBetweenRegisters { dst, src } => { SixteenBitLoadInstruction::LoadBetweenRegisters { dst, src } => {
let value = self.registers.get_16bit_register(src); let value = self.registers.get_16bit_register(src);
self.registers.set_16bit_register(dst, value); self.registers.set_16bit_register(dst, value);
} }
SixteenBitLoadInstruction::LDEffectiveAddress { dst, offset } => { SixteenBitLoadInstruction::LoadEffectiveAddress { dst, offset } => {
let current_sp = self let current_sp = self
.registers .registers
.get_single_16bit_register(register::SingleSixteenBit::StackPointer); .get_single_16bit_register(register::SingleSixteenBit::StackPointer);
@ -355,9 +355,9 @@ mod tests {
#[test_case(0x1E, register::SingleEightBit::E)] #[test_case(0x1E, register::SingleEightBit::E)]
#[test_case(0x26, register::SingleEightBit::H)] #[test_case(0x26, register::SingleEightBit::H)]
#[test_case(0x2E, register::SingleEightBit::L)] #[test_case(0x2E, register::SingleEightBit::L)]
fn test_load_immediate(ld_opcode: u8, expected_register: register::SingleEightBit) { fn test_load_immediate(load_opcode: u8, expected_register: register::SingleEightBit) {
let mut processor = Processor::default(); let mut processor = Processor::default();
let data = [ld_opcode, 0x23, 0x00, 0x01]; let data = [load_opcode, 0x23, 0x00, 0x01];
let (ins, extra_data) = let (ins, extra_data) =
RunnableInstruction::from_data(&data).expect("could not parse instruction"); RunnableInstruction::from_data(&data).expect("could not parse instruction");
@ -425,7 +425,7 @@ mod tests {
#[test_case(0x67, register::SingleEightBit::H, register::SingleEightBit::A)] #[test_case(0x67, register::SingleEightBit::H, register::SingleEightBit::A)]
#[test_case(0x6F, register::SingleEightBit::L, register::SingleEightBit::A)] #[test_case(0x6F, register::SingleEightBit::L, register::SingleEightBit::A)]
fn test_load_register( fn test_load_register(
ld_opcode: u8, load_opcode: u8,
dst_register: register::SingleEightBit, dst_register: register::SingleEightBit,
src_register: register::SingleEightBit, src_register: register::SingleEightBit,
) { ) {
@ -434,7 +434,7 @@ mod tests {
.registers .registers
.set_single_8bit_register(src_register, 0x45); .set_single_8bit_register(src_register, 0x45);
let data = [ld_opcode, 0x00]; let data = [load_opcode, 0x00];
let (ins, extra_data) = let (ins, extra_data) =
RunnableInstruction::from_data(&data).expect("could not parse instruction"); RunnableInstruction::from_data(&data).expect("could not parse instruction");

6
src/run/instructions/load16.rs
View File

@ -5,17 +5,17 @@ use crate::register;
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub enum SixteenBitLoadInstruction { pub enum SixteenBitLoadInstruction {
// 3.3.2.1 // 3.3.2.1
LDImmediateToRegister { LoadImmediateToRegister {
value: u16, value: u16,
dst: register::SixteenBit, dst: register::SixteenBit,
}, },
// 3.3.2.2 // 3.3.2.2
LDBetweenRegisters { LoadBetweenRegisters {
dst: register::SixteenBit, dst: register::SixteenBit,
src: register::SixteenBit, src: register::SixteenBit,
}, },
// 3.3.3.4 // 3.3.3.4
LDEffectiveAddress { LoadEffectiveAddress {
dst: register::Combined, dst: register::Combined,
offset: i8, offset: i8,
}, },

30
src/run/instructions/load8.rs
View File

@ -5,89 +5,89 @@ use crate::register;
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub enum EightBitLoadInstruction { pub enum EightBitLoadInstruction {
// 3.3.1.1 // 3.3.1.1
LDImmediateToRegister { LoadImmediateToRegister {
value: u8, value: u8,
register: register::SingleEightBit, register: register::SingleEightBit,
}, },
// 3.3.1.2, excluding the (hl) instructions, 3.3.1.3, excluding the (nn) instructions // 3.3.1.2, excluding the (hl) instructions, 3.3.1.3, excluding the (nn) instructions
// and 3.3.1.4 excluding the (nn) instructions // and 3.3.1.4 excluding the (nn) instructions
LDBetweenRegisters { LoadBetweenRegisters {
dst: register::SingleEightBit, dst: register::SingleEightBit,
src: register::SingleEightBit, src: register::SingleEightBit,
}, },
// 3.3.1.2/3.3.1.3, only the loading from (nn) instructions // 3.3.1.2/3.3.1.3, only the loading from (nn) instructions
LDFromRegisterAddress { LoadFromRegisterAddress {
// src, unlike some of the other instructions, is a 16bit combined register that will be // src, unlike some of the other instructions, is a 16bit combined register that will be
// dereferenced to get the value to place into the dst register // dereferenced to get the value to place into the dst register
src: register::Combined, src: register::Combined,
dst: register::SingleEightBit, dst: register::SingleEightBit,
}, },
// 3.3.1.5 - load to register relative to $FF00 (the address of the i/o registers) // 3.3.1.5 - load to register relative to $FF00 (the address of the i/o registers)
LDFromMemoryRelativeToIORegisterStart { LoadFromMemoryRelativeToIORegisterStart {
// A register whose value will be used to get the address relative to FF00 // A register whose value will be used to get the address relative to FF00
offset_register: register::SingleEightBit, offset_register: register::SingleEightBit,
dst: register::SingleEightBit, dst: register::SingleEightBit,
}, },
// 3.3.1.6 - load to memory relative to $FF00 (the address of the i/o registers) // 3.3.1.6 - load to memory relative to $FF00 (the address of the i/o registers)
LDToMemoryRelativeToIORegisterStart { LoadToMemoryRelativeToIORegisterStart {
src: register::SingleEightBit, src: register::SingleEightBit,
// A register whose value will be used to get the address relative to FF00 // A register whose value will be used to get the address relative to FF00
offset_register: register::SingleEightBit, offset_register: register::SingleEightBit,
}, },
// 3.3.1.20 // 3.3.1.20
LDFromMemoryRelativeToIORegisterStartByImmediate { LoadFromMemoryRelativeToIORegisterStartByImmediate {
dst: register::SingleEightBit, dst: register::SingleEightBit,
offset: u8, offset: u8,
}, },
// 3.3.1.19 // 3.3.1.19
LDToMemoryRelativeToIORegisterStartByImmediate { LoadToMemoryRelativeToIORegisterStartByImmediate {
offset: u8, offset: u8,
src: register::SingleEightBit, src: register::SingleEightBit,
}, },
LDFromImmediateAddress { LoadFromImmediateAddress {
src_address: u16, src_address: u16,
dst: register::SingleEightBit, dst: register::SingleEightBit,
}, },
// 3.3.1.2, only the loading to (hl) instructions // 3.3.1.2, only the loading to (hl) instructions
// 3.3.1.4, only the loading to (nn) instructions // 3.3.1.4, only the loading to (nn) instructions
LDToRegisterAddress { LoadToRegisterAddress {
src: register::SingleEightBit, src: register::SingleEightBit,
// dst, unlike some other instructions, is a 16bit combined register that holds // dst, unlike some other instructions, is a 16bit combined register that holds
// the address we will write the value to // the address we will write the value to
dst: register::Combined, dst: register::Combined,
}, },
// 3.3.1.4, only the loading to (nn) immediate instrution // 3.3.1.4, only the loading to (nn) immediate instrution
LDToImmediateAddress { LoadToImmediateAddress {
src: register::SingleEightBit, src: register::SingleEightBit,
dst_address: u16, dst_address: u16,
}, },
// 3.3.1.2, but the (hl), n instruction [why is this in this section? it's so out of place] // 3.3.1.2, but the (hl), n instruction [why is this in this section? it's so out of place]
LDnToHLAddress { LoadnToHLAddress {
value: u8, value: u8,
}, },
// 3.3.1.{7,8,9} // 3.3.1.{7,8,9}
LDFromRegisterAddressThenDec { LoadFromRegisterAddressThenDec {
// The src, unlike some other destination instructions, refers to a register // The src, unlike some other destination instructions, refers to a register
// whose address will be dereferenced (and then decremented after the load) // whose address will be dereferenced (and then decremented after the load)
src: register::Combined, src: register::Combined,
dst: register::SingleEightBit, dst: register::SingleEightBit,
}, },
// 3.3.1.{13,14,15} // 3.3.1.{13,14,15}
LDFromRegisterAddressThenInc { LoadFromRegisterAddressThenInc {
// The src, unlike some other destination instructions, refers to a register // The src, unlike some other destination instructions, refers to a register
// whose address will be dereferenced (and then incremented after the load) // whose address will be dereferenced (and then incremented after the load)
src: register::Combined, src: register::Combined,
dst: register::SingleEightBit, dst: register::SingleEightBit,
}, },
// 3.3.1.{10,11,12} // 3.3.1.{10,11,12}
LDToRegisterAddressThenDec { LoadToRegisterAddressThenDec {
src: register::SingleEightBit, src: register::SingleEightBit,
// The destination, unlike some other destination instructions, refers to a register // The destination, unlike some other destination instructions, refers to a register
// whose address will be dereferenced (and then decremented after the load) // whose address will be dereferenced (and then decremented after the load)
dst: register::Combined, dst: register::Combined,
}, },
// 3.3.1.{16,17,18} // 3.3.1.{16,17,18}
LDToRegisterAddressThenInc { LoadToRegisterAddressThenInc {
src: register::SingleEightBit, src: register::SingleEightBit,
// The destination, unlike some other destination instructions, refers to a register // The destination, unlike some other destination instructions, refers to a register
// whose address will be dereferenced (and then incremented after the load) // whose address will be dereferenced (and then incremented after the load)

4
src/run/parse/load16/immediate.rs
View File

@ -45,7 +45,7 @@ fn make_load_immediate_data(dst: register::SixteenBit, data: &[u8]) -> ParseResu
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::SixteenBitLoad( instruction: Instruction::SixteenBitLoad(
SixteenBitLoadInstruction::LDImmediateToRegister { value, dst }, SixteenBitLoadInstruction::LoadImmediateToRegister { value, dst },
), ),
cycles: 12, cycles: 12,
}, },
@ -75,7 +75,7 @@ fn make_load_effective_address(dst: register::Combined, data: &[u8]) -> ParseRes
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::SixteenBitLoad( instruction: Instruction::SixteenBitLoad(
SixteenBitLoadInstruction::LDEffectiveAddress { SixteenBitLoadInstruction::LoadEffectiveAddress {
dst, dst,
offset: signed_value, offset: signed_value,
}, },

6
src/run/parse/load16/transfer.rs
View File

@ -13,7 +13,7 @@ impl OpcodeParser for Between16BitRegisterParser {
fn parse_opcode(data: &[u8]) -> ParseResult { fn parse_opcode(data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
match opcode { match opcode {
0xF9 => make_ld_between_register_data( 0xF9 => make_load_between_register_data(
register::SixteenBit::Single(register::SingleSixteenBit::StackPointer), register::SixteenBit::Single(register::SingleSixteenBit::StackPointer),
register::SixteenBit::Combined(register::Combined::HL), register::SixteenBit::Combined(register::Combined::HL),
data, data,
@ -23,7 +23,7 @@ impl OpcodeParser for Between16BitRegisterParser {
} }
} }
fn make_ld_between_register_data( fn make_load_between_register_data(
dst: register::SixteenBit, dst: register::SixteenBit,
src: register::SixteenBit, src: register::SixteenBit,
data: &[u8], data: &[u8],
@ -33,7 +33,7 @@ fn make_ld_between_register_data(
( (
RunnableInstruction { RunnableInstruction {
instruction: Instruction::SixteenBitLoad( instruction: Instruction::SixteenBitLoad(
SixteenBitLoadInstruction::LDBetweenRegisters { dst, src }, SixteenBitLoadInstruction::LoadBetweenRegisters { dst, src },
), ),
cycles: 4, cycles: 4,
}, },

2
src/run/parse/load8/immediate.rs
View File

@ -36,7 +36,7 @@ fn make_load_immediate_data(register: register::SingleEightBit, data: &[u8]) ->
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDImmediateToRegister { EightBitLoadInstruction::LoadImmediateToRegister {
register, register,
value: *value, value: *value,
}, },

169
src/run/parse/load8/memory.rs
View File

@ -34,31 +34,31 @@ fn parse_load_from_register_to_address(data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
match opcode { match opcode {
0x02 => { 0x02 => {
make_ld_to_register_address(register::Combined::BC, register::SingleEightBit::A, data) make_load_to_register_address(register::Combined::BC, register::SingleEightBit::A, data)
} }
0x12 => { 0x12 => {
make_ld_to_register_address(register::Combined::DE, register::SingleEightBit::A, data) make_load_to_register_address(register::Combined::DE, register::SingleEightBit::A, data)
} }
0x70 => { 0x70 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::B, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::B, data)
} }
0x71 => { 0x71 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::C, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::C, data)
} }
0x72 => { 0x72 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::D, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::D, data)
} }
0x73 => { 0x73 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::E, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::E, data)
} }
0x74 => { 0x74 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::H, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::H, data)
} }
0x75 => { 0x75 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::L, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::L, data)
} }
0x77 => { 0x77 => {
make_ld_to_register_address(register::Combined::HL, register::SingleEightBit::A, data) make_load_to_register_address(register::Combined::HL, register::SingleEightBit::A, data)
} }
_ => Err(Error::UnknownOpcode(opcode)), _ => Err(Error::UnknownOpcode(opcode)),
} }
@ -67,49 +67,67 @@ fn parse_load_from_register_to_address(data: &[u8]) -> ParseResult {
fn parse_load_from_address_to_register(data: &[u8]) -> ParseResult { fn parse_load_from_address_to_register(data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
match opcode { match opcode {
0x0A => { 0x0A => make_load_from_register_address(
make_ld_from_register_address(register::SingleEightBit::A, register::Combined::BC, data) register::SingleEightBit::A,
} register::Combined::BC,
0x1A => { data,
make_ld_from_register_address(register::SingleEightBit::A, register::Combined::DE, data) ),
} 0x1A => make_load_from_register_address(
0x46 => { register::SingleEightBit::A,
make_ld_from_register_address(register::SingleEightBit::B, register::Combined::HL, data) register::Combined::DE,
} data,
0x4E => { ),
make_ld_from_register_address(register::SingleEightBit::C, register::Combined::HL, data) 0x46 => make_load_from_register_address(
} register::SingleEightBit::B,
0x56 => { register::Combined::HL,
make_ld_from_register_address(register::SingleEightBit::D, register::Combined::HL, data) data,
} ),
0x5E => { 0x4E => make_load_from_register_address(
make_ld_from_register_address(register::SingleEightBit::E, register::Combined::HL, data) register::SingleEightBit::C,
} register::Combined::HL,
0x66 => { data,
make_ld_from_register_address(register::SingleEightBit::H, register::Combined::HL, data) ),
} 0x56 => make_load_from_register_address(
0x6E => { register::SingleEightBit::D,
make_ld_from_register_address(register::SingleEightBit::L, register::Combined::HL, data) register::Combined::HL,
} data,
0x7E => { ),
make_ld_from_register_address(register::SingleEightBit::A, register::Combined::HL, data) 0x5E => make_load_from_register_address(
} register::SingleEightBit::E,
register::Combined::HL,
data,
),
0x66 => make_load_from_register_address(
register::SingleEightBit::H,
register::Combined::HL,
data,
),
0x6E => make_load_from_register_address(
register::SingleEightBit::L,
register::Combined::HL,
data,
),
0x7E => make_load_from_register_address(
register::SingleEightBit::A,
register::Combined::HL,
data,
),
0xF2 => make_ld_from_memory_relative_to_io_register_start( 0xF2 => make_load_from_memory_relative_to_io_register_start(
register::SingleEightBit::C, register::SingleEightBit::C,
register::SingleEightBit::A, register::SingleEightBit::A,
data, data,
), ),
0xE2 => make_ld_to_memory_relative_to_io_register_start( 0xE2 => make_load_to_memory_relative_to_io_register_start(
register::SingleEightBit::C, register::SingleEightBit::C,
register::SingleEightBit::A, register::SingleEightBit::A,
data, data,
), ),
0xF0 => make_ld_from_memory_relative_to_io_register_start_by_immediate( 0xF0 => make_load_from_memory_relative_to_io_register_start_by_immediate(
register::SingleEightBit::A, register::SingleEightBit::A,
data, data,
), ),
0xE0 => make_ld_to_memory_relative_to_io_register_start_by_immediate( 0xE0 => make_load_to_memory_relative_to_io_register_start_by_immediate(
register::SingleEightBit::A, register::SingleEightBit::A,
data, data,
), ),
@ -121,9 +139,9 @@ fn parse_load_from_address_to_register(data: &[u8]) -> ParseResult {
fn parse_load_immediate_instructions(data: &[u8]) -> ParseResult { fn parse_load_immediate_instructions(data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
match opcode { match opcode {
0x36 => make_ld_n_to_hl_address(data), 0x36 => make_load_n_to_hl_address(data),
0xFA => make_ld_from_immediate_address(register::SingleEightBit::A, data), 0xFA => make_load_from_immediate_address(register::SingleEightBit::A, data),
0xEA => make_ld_to_immediate_address(register::SingleEightBit::A, data), 0xEA => make_load_to_immediate_address(register::SingleEightBit::A, data),
_ => Err(Error::UnknownOpcode(opcode)), _ => Err(Error::UnknownOpcode(opcode)),
} }
} }
@ -131,35 +149,35 @@ fn parse_load_immediate_instructions(data: &[u8]) -> ParseResult {
fn parse_load_from_register_to_address_and_do_arithmetic(data: &[u8]) -> ParseResult { fn parse_load_from_register_to_address_and_do_arithmetic(data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
match opcode { match opcode {
0x32 => make_ld_to_address_and_do_arithmetic( 0x32 => make_load_to_address_and_do_arithmetic(
register::Combined::HL, register::Combined::HL,
register::SingleEightBit::A, register::SingleEightBit::A,
|dst, src| EightBitLoadInstruction::LDToRegisterAddressThenDec { dst, src }, |dst, src| EightBitLoadInstruction::LoadToRegisterAddressThenDec { dst, src },
data, data,
), ),
0x22 => make_ld_to_address_and_do_arithmetic( 0x22 => make_load_to_address_and_do_arithmetic(
register::Combined::HL, register::Combined::HL,
register::SingleEightBit::A, register::SingleEightBit::A,
|dst, src| EightBitLoadInstruction::LDToRegisterAddressThenInc { dst, src }, |dst, src| EightBitLoadInstruction::LoadToRegisterAddressThenInc { dst, src },
data, data,
), ),
0x3A => make_ld_from_address_and_do_arithmetic( 0x3A => make_load_from_address_and_do_arithmetic(
register::SingleEightBit::A, register::SingleEightBit::A,
register::Combined::HL, register::Combined::HL,
|dst, src| EightBitLoadInstruction::LDFromRegisterAddressThenDec { dst, src }, |dst, src| EightBitLoadInstruction::LoadFromRegisterAddressThenDec { dst, src },
data, data,
), ),
0x2A => make_ld_from_address_and_do_arithmetic( 0x2A => make_load_from_address_and_do_arithmetic(
register::SingleEightBit::A, register::SingleEightBit::A,
register::Combined::HL, register::Combined::HL,
|dst, src| EightBitLoadInstruction::LDFromRegisterAddressThenInc { dst, src }, |dst, src| EightBitLoadInstruction::LoadFromRegisterAddressThenInc { dst, src },
data, data,
), ),
_ => Err(Error::UnknownOpcode(opcode)), _ => Err(Error::UnknownOpcode(opcode)),
} }
} }
fn make_ld_from_register_address( fn make_load_from_register_address(
dst: register::SingleEightBit, dst: register::SingleEightBit,
src: register::Combined, src: register::Combined,
data: &[u8], data: &[u8],
@ -169,7 +187,7 @@ fn make_ld_from_register_address(
( (
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDFromRegisterAddress { src, dst }, EightBitLoadInstruction::LoadFromRegisterAddress { src, dst },
), ),
cycles: 8, cycles: 8,
}, },
@ -179,7 +197,7 @@ fn make_ld_from_register_address(
.ok_or(Error::NoData) .ok_or(Error::NoData)
} }
fn make_ld_to_register_address( fn make_load_to_register_address(
dst: register::Combined, dst: register::Combined,
src: register::SingleEightBit, src: register::SingleEightBit,
data: &[u8], data: &[u8],
@ -189,7 +207,7 @@ fn make_ld_to_register_address(
( (
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDToRegisterAddress { src, dst }, EightBitLoadInstruction::LoadToRegisterAddress { src, dst },
), ),
cycles: 8, cycles: 8,
}, },
@ -199,7 +217,7 @@ fn make_ld_to_register_address(
.ok_or(Error::NoData) .ok_or(Error::NoData)
} }
fn make_ld_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) -> ParseResult { fn make_load_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?; let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?;
@ -208,7 +226,7 @@ fn make_ld_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) ->
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDFromImmediateAddress { src_address, dst }, EightBitLoadInstruction::LoadFromImmediateAddress { src_address, dst },
), ),
cycles: 16, cycles: 16,
}, },
@ -217,7 +235,7 @@ fn make_ld_from_immediate_address(dst: register::SingleEightBit, data: &[u8]) ->
)) ))
} }
fn make_ld_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> ParseResult { fn make_load_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?; let args = data.get(1..=2).ok_or(Error::NotEnoughArgs(opcode))?;
@ -225,10 +243,9 @@ fn make_ld_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> P
let dst_address = u16::from_le_bytes([args[0], args[1]]); let dst_address = u16::from_le_bytes([args[0], args[1]]);
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad(EightBitLoadInstruction::LDToImmediateAddress { instruction: Instruction::EightBitLoad(
src, EightBitLoadInstruction::LoadToImmediateAddress { src, dst_address },
dst_address, ),
}),
cycles: 16, cycles: 16,
}, },
// This can't fail if get(1..=2) passed // This can't fail if get(1..=2) passed
@ -236,12 +253,12 @@ fn make_ld_to_immediate_address(src: register::SingleEightBit, data: &[u8]) -> P
)) ))
} }
fn make_ld_n_to_hl_address(data: &[u8]) -> ParseResult { fn make_load_n_to_hl_address(data: &[u8]) -> ParseResult {
let opcode = parse::get_opcode_from_data(data)?; let opcode = parse::get_opcode_from_data(data)?;
let value = data.get(1).ok_or(Error::NotEnoughArgs(opcode))?; let value = data.get(1).ok_or(Error::NotEnoughArgs(opcode))?;
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad(EightBitLoadInstruction::LDnToHLAddress { instruction: Instruction::EightBitLoad(EightBitLoadInstruction::LoadnToHLAddress {
value: *value, value: *value,
}), }),
cycles: 12, cycles: 12,
@ -251,7 +268,7 @@ fn make_ld_n_to_hl_address(data: &[u8]) -> ParseResult {
)) ))
} }
fn make_ld_from_memory_relative_to_io_register_start( fn make_load_from_memory_relative_to_io_register_start(
offset_register: register::SingleEightBit, offset_register: register::SingleEightBit,
dst: register::SingleEightBit, dst: register::SingleEightBit,
data: &[u8], data: &[u8],
@ -261,7 +278,7 @@ fn make_ld_from_memory_relative_to_io_register_start(
( (
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStart { EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStart {
offset_register, offset_register,
dst, dst,
}, },
@ -275,7 +292,7 @@ fn make_ld_from_memory_relative_to_io_register_start(
.ok_or(Error::NoData) .ok_or(Error::NoData)
} }
fn make_ld_to_memory_relative_to_io_register_start( fn make_load_to_memory_relative_to_io_register_start(
offset_register: register::SingleEightBit, offset_register: register::SingleEightBit,
src: register::SingleEightBit, src: register::SingleEightBit,
data: &[u8], data: &[u8],
@ -285,7 +302,7 @@ fn make_ld_to_memory_relative_to_io_register_start(
( (
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStart { EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStart {
src, src,
offset_register, offset_register,
}, },
@ -299,7 +316,7 @@ fn make_ld_to_memory_relative_to_io_register_start(
.ok_or(Error::NoData) .ok_or(Error::NoData)
} }
fn make_ld_to_memory_relative_to_io_register_start_by_immediate( fn make_load_to_memory_relative_to_io_register_start_by_immediate(
src: register::SingleEightBit, src: register::SingleEightBit,
data: &[u8], data: &[u8],
) -> ParseResult { ) -> ParseResult {
@ -309,7 +326,7 @@ fn make_ld_to_memory_relative_to_io_register_start_by_immediate(
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDToMemoryRelativeToIORegisterStartByImmediate { EightBitLoadInstruction::LoadToMemoryRelativeToIORegisterStartByImmediate {
src, src,
offset: *value, offset: *value,
}, },
@ -321,7 +338,7 @@ fn make_ld_to_memory_relative_to_io_register_start_by_immediate(
)) ))
} }
fn make_ld_from_memory_relative_to_io_register_start_by_immediate( fn make_load_from_memory_relative_to_io_register_start_by_immediate(
dst: register::SingleEightBit, dst: register::SingleEightBit,
data: &[u8], data: &[u8],
) -> ParseResult { ) -> ParseResult {
@ -331,7 +348,7 @@ fn make_ld_from_memory_relative_to_io_register_start_by_immediate(
Ok(( Ok((
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDFromMemoryRelativeToIORegisterStartByImmediate { EightBitLoadInstruction::LoadFromMemoryRelativeToIORegisterStartByImmediate {
offset: *value, offset: *value,
dst, dst,
}, },
@ -343,9 +360,9 @@ fn make_ld_from_memory_relative_to_io_register_start_by_immediate(
)) ))
} }
/// `make_ld_to_address_and_do_arithmetic` will make one of the instructions that load to memory and either increment /// `make_load_to_address_and_do_arithmetic` will make one of the instructions that load to memory and either increment
/// or decerement. The instruction itself will be produced by the given `make` function. /// or decerement. The instruction itself will be produced by the given `make` function.
fn make_ld_to_address_and_do_arithmetic< fn make_load_to_address_and_do_arithmetic<
F: Fn(register::Combined, register::SingleEightBit) -> EightBitLoadInstruction, F: Fn(register::Combined, register::SingleEightBit) -> EightBitLoadInstruction,
>( >(
dst: register::Combined, dst: register::Combined,
@ -356,9 +373,9 @@ fn make_ld_to_address_and_do_arithmetic<
make_load_and_do_arithmetic(|| make(dst, src), data) make_load_and_do_arithmetic(|| make(dst, src), data)
} }
/// `make_ld_to_address_and_do_arithmetic` will make one of the instructions that load from memory and either increment /// `make_load_to_address_and_do_arithmetic` will make one of the instructions that load from memory and either increment
/// or decerement. The instruction itself will be produced by the given `make` function. /// or decerement. The instruction itself will be produced by the given `make` function.
fn make_ld_from_address_and_do_arithmetic< fn make_load_from_address_and_do_arithmetic<
F: Fn(register::SingleEightBit, register::Combined) -> EightBitLoadInstruction, F: Fn(register::SingleEightBit, register::Combined) -> EightBitLoadInstruction,
>( >(
dst: register::SingleEightBit, dst: register::SingleEightBit,

2
src/run/parse/load8/transfer.rs
View File

@ -89,7 +89,7 @@ fn make_load_between_register_data(
( (
RunnableInstruction { RunnableInstruction {
instruction: Instruction::EightBitLoad( instruction: Instruction::EightBitLoad(
EightBitLoadInstruction::LDBetweenRegisters { dst, src }, EightBitLoadInstruction::LoadBetweenRegisters { dst, src },
), ),
cycles: 4, cycles: 4,
}, },