diff --git a/src/cpu/parse/arith8/sub.rs b/src/cpu/parse/arith8/sub.rs
index 62ebaf4..10dc5da 100644
--- a/src/cpu/parse/arith8/sub.rs
+++ b/src/cpu/parse/arith8/sub.rs
@@ -38,6 +38,9 @@ impl OpcodeParser for EightBitSubParser {
             0x9D => Ok(build_sub_register_from_a_with_carry_data(
                 register::SingleEightBit::L,
             )),
+            0x9F => Ok(build_sub_register_from_a_with_carry_data(
+                register::SingleEightBit::A,
+            )),
             _ => Err(Error::UnknownOpcode(opcode)),
         }
     }
diff --git a/tests/cpu/arith8.rs b/tests/cpu/arith8.rs
index 1f11b14..85ba89f 100644
--- a/tests/cpu/arith8.rs
+++ b/tests/cpu/arith8.rs
@@ -826,3 +826,59 @@ fn test_sub_register_from_carry_from_a_flags(
         (register::Flag::Carry, expected_flags.carry),
     );
 }
+
+#[test_case(0, 0; "subtract from itself")]
+#[test_case(1, 0xFF; "subtract from itself with carry bit")]
+fn test_sub_a_register_from_itself_with_carry_value(carry_bit: u8, expected: u8) {
+    let mut processor = Processor::default();
+    processor.registers.a = 0xEE;
+    processor
+        .registers
+        .set_flag_bit(register::Flag::Carry, carry_bit);
+
+    let data = [0x9F, 0x01];
+    let (ins, extra_data) =
+        RunnableInstruction::from_data(&data).expect("could not parse instruction");
+    assert_eq!(extra_data, &[0x01]);
+    processor.run_instruction(&ins);
+
+    assert_eq!(expected, processor.registers.a);
+}
+
+#[test_case(0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtract from itself")]
+#[test_case(1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "subtract from itself with carry bit")]
+fn test_sub_a_register_from_itself_with_carry_flags(
+    carry_bit: u8,
+    expected_flags: AdditionOperationFlags,
+) {
+    let mut processor = Processor::default();
+    // Set all the register to the opposite we expect to ensure they all get set
+    testutil::set_opposite_of_expected_flags(
+        &mut processor,
+        (
+            expected_flags.zero,
+            0,
+            expected_flags.half_carry,
+            expected_flags.carry,
+        ),
+    );
+
+    processor.registers.a = 0xEE;
+    processor
+        .registers
+        .set_flag_bit(register::Flag::Carry, carry_bit);
+
+    let data = [0x9F, 0x01];
+    let (ins, extra_data) =
+        RunnableInstruction::from_data(&data).expect("could not parse instruction");
+    assert_eq!(extra_data, &[0x01]);
+    processor.run_instruction(&ins);
+
+    testutil::assert_flags_eq!(
+        processor,
+        (register::Flag::Zero, expected_flags.zero),
+        (register::Flag::Subtract, 1),
+        (register::Flag::HalfCarry, expected_flags.half_carry),
+        (register::Flag::Carry, expected_flags.carry),
+    );
+}
diff --git a/tests/cpu/jsmoo/testdata/disabled/9f.json b/tests/cpu/jsmoo/testdata/9f.json
similarity index 100%
rename from tests/cpu/jsmoo/testdata/disabled/9f.json
rename to tests/cpu/jsmoo/testdata/9f.json