diff --git a/src/cpu.rs b/src/cpu.rs
index 8958330..cca0a5c 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -14,7 +14,7 @@ mod run;
 pub struct Processor {
     pub registers: Registers,
     pub memory: Memory,
-    num_cycles: u64,
+    pub num_cycles: u128,
 }
 
 impl Processor {
@@ -48,7 +48,7 @@ impl Processor {
             panic!("Fatal CPU error occured: {err}")
         }
 
-        self.num_cycles += u64::from(instruction.cycles);
+        self.num_cycles += u128::from(instruction.cycles);
     }
 
     fn load_from_register_to_register_address(
diff --git a/src/cpu/parse/arith16.rs b/src/cpu/parse/arith16.rs
index c2beb42..a8711e9 100644
--- a/src/cpu/parse/arith16.rs
+++ b/src/cpu/parse/arith16.rs
@@ -53,7 +53,7 @@ fn build_add_hl_to_register_data(operand_register: SixteenBit) -> ParseOutput {
             instruction: Instruction::SixteenBitArithmetic(
                 SixteenBitArithmeticInstruction::AddRegisterToHL { operand_register },
             ),
-            cycles: 2,
+            cycles: 8,
         },
         1,
     )
@@ -65,7 +65,7 @@ fn build_inc_register_data(operand_register: SixteenBit) -> ParseOutput {
             instruction: Instruction::SixteenBitArithmetic(
                 SixteenBitArithmeticInstruction::IncrementRegister { operand_register },
             ),
-            cycles: 2,
+            cycles: 8,
         },
         1,
     )
@@ -77,7 +77,7 @@ fn build_dec_register_data(operand_register: SixteenBit) -> ParseOutput {
             instruction: Instruction::SixteenBitArithmetic(
                 SixteenBitArithmeticInstruction::DecrementRegister { operand_register },
             ),
-            cycles: 2,
+            cycles: 8,
         },
         1,
     )
diff --git a/src/cpu/parse/load16/transfer.rs b/src/cpu/parse/load16/transfer.rs
index 29e1061..d7d56c5 100644
--- a/src/cpu/parse/load16/transfer.rs
+++ b/src/cpu/parse/load16/transfer.rs
@@ -33,7 +33,7 @@ fn make_load_between_register_data(
             instruction: Instruction::SixteenBitLoad(
                 SixteenBitLoadInstruction::LoadBetweenRegisters { dst, src },
             ),
-            cycles: 4,
+            cycles: 8,
         },
         1,
     )
diff --git a/tests/cpu/jsmoo.rs b/tests/cpu/jsmoo.rs
index 983f651..f344d37 100644
--- a/tests/cpu/jsmoo.rs
+++ b/tests/cpu/jsmoo.rs
@@ -25,4 +25,5 @@ struct TestCase {
     name: String,
     initial: TestState,
     r#final: TestState,
+    cycles: Vec<serde_json::Value>
 }
diff --git a/tests/cpu/jsmoo/tests.rs b/tests/cpu/jsmoo/tests.rs
index 890acb0..e9f4d35 100644
--- a/tests/cpu/jsmoo/tests.rs
+++ b/tests/cpu/jsmoo/tests.rs
@@ -90,5 +90,8 @@ fn test_jsmoo_test(filename: &str) {
 
             assert_eq!(stored_val, value);
         }
+
+        let num_cycles_expected = test_case.cycles.len() * 4;
+        assert_eq!(u128::try_from(num_cycles_expected).unwrap(), processor.num_cycles);
     }
 }