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@ -5,7 +5,7 @@ use ferris_boi::{
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use crate::testutil;
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use crate::testutil;
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use test_case::test_case;
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use test_case::{test_case, test_matrix};
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struct AdditionOperationFlags {
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struct AdditionOperationFlags {
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zero: u8,
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zero: u8,
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@ -55,18 +55,26 @@ fn test_add_to_a_value(opcode: u8, src: register::SingleEightBit) {
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assert_eq!(30, processor.registers.a);
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assert_eq!(30, processor.registers.a);
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}
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}
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#[test_case(0x80, register::SingleEightBit::B, 0x00, 0x00, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "zero flag for zero value")]
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#[test_matrix(
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#[test_case(0x80, register::SingleEightBit::B, 0x00, 0x01, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no zero flag for non-zero value")]
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[
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#[test_case(0x81, register::SingleEightBit::C, 0x0F, 0x01, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "half carry flag")]
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(0x00, 0x00, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}),
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#[test_case(0x81, register::SingleEightBit::C, 0x80, 0x80, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 1}; "full carry flag")]
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(0x00, 0x01, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}),
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#[test_case(0x81, register::SingleEightBit::C, 0xFF, 0x01, AdditionOperationFlags{zero: 1, half_carry: 1, carry: 1}; "all flags")]
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(0x0F, 0x01, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
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// 0000 1111
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(0x80, 0x80, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 1}),
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(0xFF, 0x01, AdditionOperationFlags{zero: 1, half_carry: 1, carry: 1})
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],
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[
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(0x80, register::SingleEightBit::B),
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(0x81, register::SingleEightBit::C),
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(0x82, register::SingleEightBit::D),
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(0x83, register::SingleEightBit::E),
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(0x84, register::SingleEightBit::H),
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(0x85, register::SingleEightBit::L),
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]
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)]
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fn test_add_register_to_a_flags(
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fn test_add_register_to_a_flags(
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opcode: u8,
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(a_value, src_value, expected_flags): (u8, u8, AdditionOperationFlags),
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src: register::SingleEightBit,
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(opcode, src): (u8, register::SingleEightBit),
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a_value: u8,
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src_value: u8,
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expected_flags: AdditionOperationFlags,
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) {
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) {
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let mut processor = Processor::default();
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let mut processor = Processor::default();
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processor.registers.a = a_value;
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processor.registers.a = a_value;
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@ -224,25 +232,23 @@ fn test_add_immediate_to_a_flags(a_value: u8, n: u8, expected_flags: AdditionOpe
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);
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);
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}
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}
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#[test_case(0x88, 0x12, 0, register::SingleEightBit::B, 0x5, 0x17; "no carry to register b")]
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#[test_matrix(
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#[test_case(0x88, 0x12, 1, register::SingleEightBit::B, 0x5, 0x18; "carry to register b")]
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[
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#[test_case(0x89, 0x12, 0, register::SingleEightBit::C, 0x5, 0x17; "no carry to register c")]
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(0x88, register::SingleEightBit::B),
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#[test_case(0x89, 0x12, 1, register::SingleEightBit::C, 0x5, 0x18; "carry to register c")]
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(0x89, register::SingleEightBit::C),
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#[test_case(0x8A, 0x12, 0, register::SingleEightBit::D, 0x5, 0x17; "no carry to register d")]
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(0x8A, register::SingleEightBit::D),
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#[test_case(0x8A, 0x12, 1, register::SingleEightBit::D, 0x5, 0x18; "carry to register d")]
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(0x8B, register::SingleEightBit::E),
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#[test_case(0x8B, 0x12, 0, register::SingleEightBit::E, 0x5, 0x17; "no carry to register e")]
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(0x8C, register::SingleEightBit::H),
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#[test_case(0x8B, 0x12, 1, register::SingleEightBit::E, 0x5, 0x18; "carry to register e")]
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(0x8D, register::SingleEightBit::L),
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#[test_case(0x8C, 0x12, 0, register::SingleEightBit::H, 0x5, 0x17; "no carry to register h")]
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],
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#[test_case(0x8C, 0x12, 1, register::SingleEightBit::H, 0x5, 0x18; "carry to register h")]
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[
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#[test_case(0x8D, 0x12, 0, register::SingleEightBit::L, 0x5, 0x17; "no carry to register l")]
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(0x12, 0x05, 0, 0x17),
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#[test_case(0x8D, 0x12, 1, register::SingleEightBit::L, 0x5, 0x18; "carry to register l")]
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(0x12, 0x05, 1, 0x18)
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]
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)]
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fn test_add_register_with_carry_to_a_value(
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fn test_add_register_with_carry_to_a_value(
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opcode: u8,
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(opcode, operand_register): (u8, register::SingleEightBit),
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initial_value: u8,
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(initial_value, operand, carry_bit, expected_value): (u8, u8, u8, u8),
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carry_bit: u8,
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operand_register: register::SingleEightBit,
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operand: u8,
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expected_value: u8,
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) {
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) {
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let mut processor = Processor::default();
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let mut processor = Processor::default();
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processor.registers.a = initial_value;
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processor.registers.a = initial_value;
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@ -262,74 +268,37 @@ fn test_add_register_with_carry_to_a_value(
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assert_eq!(expected_value, processor.registers.a);
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assert_eq!(expected_value, processor.registers.a);
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}
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}
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// these parameters are like impossible to read but I can't think of a nicer way to do this right now
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#[test_matrix(
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// B register
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[
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#[test_case(0x88, 0x12, 0, register::SingleEightBit::B, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register b")]
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(0x88, register::SingleEightBit::B),
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#[test_case(0x88, 0x12, 1, register::SingleEightBit::B, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register b")]
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(0x89, register::SingleEightBit::C),
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#[test_case(0x88, 0x00, 0, register::SingleEightBit::B, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "no carry bit set, zero operands result in zero flag set, register b")]
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(0x8A, register::SingleEightBit::D),
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#[test_case(0x88, 0x00, 1, register::SingleEightBit::B, 0x0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, zero operands result in no zero flag set, register b")]
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(0x8B, register::SingleEightBit::E),
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#[test_case(0x88, 0x0F, 0, register::SingleEightBit::B, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, half carry, register b")]
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(0x8C, register::SingleEightBit::H),
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#[test_case(0x88, 0x0F, 1, register::SingleEightBit::B, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, half carry, register b")]
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(0x8D, register::SingleEightBit::L),
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#[test_case(0x88, 0x0F, 0, register::SingleEightBit::B, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, full carry, register b")]
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],
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#[test_case(0x88, 0x0F, 1, register::SingleEightBit::B, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, full carry, register b")]
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[
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#[test_case(0x88, 0xFF, 1, register::SingleEightBit::B, 0xFF, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "carry bit, both carries, register b")]
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(0x12, 0x05, 0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}),
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// C register
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(0x12, 0x05, 1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}),
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#[test_case(0x89, 0x12, 0, register::SingleEightBit::C, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register c")]
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#[test_case(0x89, 0x12, 1, register::SingleEightBit::C, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register c")]
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(0x00, 0x00, 0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}),
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#[test_case(0x89, 0x00, 0, register::SingleEightBit::C, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "no carry bit set, zero operands result in zero flag set, register c")]
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(0x00, 0x00, 1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}),
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#[test_case(0x89, 0x00, 1, register::SingleEightBit::C, 0x0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, zero operands result in no zero flag set, register c")]
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#[test_case(0x89, 0x0F, 0, register::SingleEightBit::C, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, half carry, register c")]
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(0x0F, 0x01, 0, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
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#[test_case(0x89, 0x0F, 1, register::SingleEightBit::C, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, half carry, register c")]
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(0x0F, 0x01, 1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
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#[test_case(0x89, 0x0F, 0, register::SingleEightBit::C, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, full carry, register c")]
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(0x0F, 0x0F, 0, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
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#[test_case(0x89, 0x0F, 1, register::SingleEightBit::C, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, full carry, register c")]
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(0x0F, 0x0F, 1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
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#[test_case(0x89, 0xFF, 1, register::SingleEightBit::C, 0xFF, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "carry bit, both carries, register c")]
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// D register
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(0x80, 0x82, 0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}),
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#[test_case(0x8A, 0x12, 0, register::SingleEightBit::D, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register d")]
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(0x80, 0x82, 1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}),
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#[test_case(0x8A, 0x12, 1, register::SingleEightBit::D, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register d")]
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#[test_case(0x8A, 0x00, 0, register::SingleEightBit::D, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "no carry bit set, zero operands result in zero flag set, register d")]
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(0x0F, 0xFF, 0, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}),
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#[test_case(0x8A, 0x00, 1, register::SingleEightBit::D, 0x0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, zero operands result in no zero flag set, register d")]
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(0x7F, 0x80, 1, AdditionOperationFlags{zero: 1, half_carry: 1, carry: 1}),
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#[test_case(0x8A, 0x0F, 0, register::SingleEightBit::D, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, half carry, register d")]
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]
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#[test_case(0x8A, 0x0F, 1, register::SingleEightBit::D, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, half carry, register d")]
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) ]
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#[test_case(0x8A, 0x0F, 0, register::SingleEightBit::D, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, full carry, register d")]
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#[test_case(0x8A, 0x0F, 1, register::SingleEightBit::D, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, full carry, register d")]
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#[test_case(0x8A, 0xFF, 1, register::SingleEightBit::D, 0xFF, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "carry bit, both carries, register d")]
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// E register
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#[test_case(0x8B, 0x12, 0, register::SingleEightBit::E, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register e")]
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#[test_case(0x8B, 0x12, 1, register::SingleEightBit::E, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register e")]
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#[test_case(0x8B, 0x00, 0, register::SingleEightBit::E, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "no carry bit set, zero operands result in zero flag set, register e")]
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#[test_case(0x8B, 0x00, 1, register::SingleEightBit::E, 0x0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, zero operands result in no zero flag set, register e")]
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#[test_case(0x8B, 0x0F, 0, register::SingleEightBit::E, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, half carry, register e")]
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#[test_case(0x8B, 0x0F, 1, register::SingleEightBit::E, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, half carry, register e")]
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#[test_case(0x8B, 0x0F, 0, register::SingleEightBit::E, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, full carry, register e")]
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#[test_case(0x8B, 0x0F, 1, register::SingleEightBit::E, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, full carry, register e")]
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#[test_case(0x8B, 0xFF, 1, register::SingleEightBit::E, 0xFF, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "carry bit, both carries, register e")]
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// H register
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#[test_case(0x8C, 0x12, 0, register::SingleEightBit::H, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register h")]
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#[test_case(0x8C, 0x12, 1, register::SingleEightBit::H, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register h")]
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#[test_case(0x8C, 0x00, 0, register::SingleEightBit::H, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "no carry bit set, zero operands result in zero flag set, register h")]
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#[test_case(0x8C, 0x00, 1, register::SingleEightBit::H, 0x0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, zero operands result in no zero flag set, register h")]
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#[test_case(0x8C, 0x0F, 0, register::SingleEightBit::H, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, half carry, register h")]
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#[test_case(0x8C, 0x0F, 1, register::SingleEightBit::H, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, half carry, register h")]
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#[test_case(0x8C, 0x0F, 0, register::SingleEightBit::H, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, full carry, register h")]
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#[test_case(0x8C, 0x0F, 1, register::SingleEightBit::H, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, full carry, register h")]
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#[test_case(0x8C, 0xFF, 1, register::SingleEightBit::H, 0xFF, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "carry bit, both carries, register h")]
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// L register
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#[test_case(0x8D, 0x12, 0, register::SingleEightBit::L, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x12, 1, register::SingleEightBit::L, 0x5, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x00, 0, register::SingleEightBit::L, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "no carry bit set, zero operands result in zero flag set, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x00, 1, register::SingleEightBit::L, 0x0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, zero operands result in no zero flag set, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x0F, 0, register::SingleEightBit::L, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, half carry, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x0F, 1, register::SingleEightBit::L, 0x1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, half carry, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x0F, 0, register::SingleEightBit::L, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit, full carry, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0x0F, 1, register::SingleEightBit::L, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit, full carry, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x8D, 0xFF, 1, register::SingleEightBit::L, 0xFF, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 1}; "carry bit, both carries, register l")]
|
|
|
|
|
|
|
|
fn test_add_register_with_carry_to_a_flags(
|
|
|
|
fn test_add_register_with_carry_to_a_flags(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
initial_value: u8,
|
|
|
|
(initial_value, operand, carry_bit, expected_flags): (u8, u8, u8, AdditionOperationFlags),
|
|
|
|
carry_bit: u8,
|
|
|
|
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
expected_flags: AdditionOperationFlags,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor.registers.a = initial_value;
|
|
|
|
processor.registers.a = initial_value;
|
|
|
|
@ -572,18 +541,23 @@ fn test_add_hl_addr_to_a_with_carry_flags(
|
|
|
|
);
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0x90, 0xFF, 0x0F, register::SingleEightBit::B, 0xF0; "subtract B")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x91, 0xFF, 0x0F, register::SingleEightBit::C, 0xF0; "subtract C")]
|
|
|
|
[
|
|
|
|
#[test_case(0x92, 0xFF, 0x0F, register::SingleEightBit::D, 0xF0; "subtract D")]
|
|
|
|
(0x90, register::SingleEightBit::B),
|
|
|
|
#[test_case(0x93, 0xFF, 0x0F, register::SingleEightBit::E, 0xF0; "subtract E")]
|
|
|
|
(0x91, register::SingleEightBit::C),
|
|
|
|
#[test_case(0x94, 0xFF, 0x0F, register::SingleEightBit::H, 0xF0; "subtract H")]
|
|
|
|
(0x92, register::SingleEightBit::D),
|
|
|
|
#[test_case(0x95, 0xFF, 0x0F, register::SingleEightBit::L, 0xF0; "subtract L")]
|
|
|
|
(0x93, register::SingleEightBit::E),
|
|
|
|
|
|
|
|
(0x94, register::SingleEightBit::H),
|
|
|
|
|
|
|
|
(0x95, register::SingleEightBit::L),
|
|
|
|
|
|
|
|
],
|
|
|
|
|
|
|
|
[
|
|
|
|
|
|
|
|
(0xFF, 0x0F, 0xF0),
|
|
|
|
|
|
|
|
(0x00, 0x03, 0xFD),
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_sub_register_from_a_value(
|
|
|
|
fn test_sub_register_from_a_value(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, expected): (u8, u8, u8),
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
expected: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor.registers.a = a_value;
|
|
|
|
processor.registers.a = a_value;
|
|
|
|
@ -601,36 +575,25 @@ fn test_sub_register_from_a_value(
|
|
|
|
assert_eq!(processor.registers.a, expected);
|
|
|
|
assert_eq!(processor.registers.a, expected);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0x90, 0xFF, 0x0F, register::SingleEightBit::B, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 0 }; "no flags from B")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x90, 0xF0, 0x0F, register::SingleEightBit::B, AdditionOperationFlags { zero: 0, half_carry: 1, carry: 0 }; "half carry from B")]
|
|
|
|
[
|
|
|
|
#[test_case(0x90, 0x0F, 0xF0, register::SingleEightBit::B, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 1 }; "full carry from B")]
|
|
|
|
(0x90, register::SingleEightBit::B),
|
|
|
|
#[test_case(0x90, 0x01, 0x01, register::SingleEightBit::B, AdditionOperationFlags { zero: 1, half_carry: 0, carry: 0 }; "zero from B")]
|
|
|
|
(0x91, register::SingleEightBit::C),
|
|
|
|
#[test_case(0x91, 0xFF, 0x0F, register::SingleEightBit::C, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 0 }; "no flags from C")]
|
|
|
|
(0x92, register::SingleEightBit::D),
|
|
|
|
#[test_case(0x91, 0xF0, 0x0F, register::SingleEightBit::C, AdditionOperationFlags { zero: 0, half_carry: 1, carry: 0 }; "half carry from C")]
|
|
|
|
(0x93, register::SingleEightBit::E),
|
|
|
|
#[test_case(0x91, 0x0F, 0xF0, register::SingleEightBit::C, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 1 }; "full carry from C")]
|
|
|
|
(0x94, register::SingleEightBit::H),
|
|
|
|
#[test_case(0x91, 0x01, 0x01, register::SingleEightBit::C, AdditionOperationFlags { zero: 1, half_carry: 0, carry: 0 }; "zero from C")]
|
|
|
|
(0x95, register::SingleEightBit::L),
|
|
|
|
#[test_case(0x92, 0xFF, 0x0F, register::SingleEightBit::D, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 0 }; "no flags from D")]
|
|
|
|
],
|
|
|
|
#[test_case(0x92, 0xF0, 0x0F, register::SingleEightBit::D, AdditionOperationFlags { zero: 0, half_carry: 1, carry: 0 }; "half carry from D")]
|
|
|
|
[
|
|
|
|
#[test_case(0x92, 0x0F, 0xF0, register::SingleEightBit::D, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 1 }; "full carry from D")]
|
|
|
|
(0xFF, 0x0F, AdditionOperationFlags{ zero: 0, half_carry: 0, carry: 0 }),
|
|
|
|
#[test_case(0x92, 0x01, 0x01, register::SingleEightBit::D, AdditionOperationFlags { zero: 1, half_carry: 0, carry: 0 }; "zero from D")]
|
|
|
|
(0xF0, 0x0F, AdditionOperationFlags{ zero: 0, half_carry: 1, carry: 0 }),
|
|
|
|
#[test_case(0x93, 0xFF, 0x0F, register::SingleEightBit::E, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 0 }; "no flags from E")]
|
|
|
|
(0x0F, 0xF0, AdditionOperationFlags{ zero: 0, half_carry: 0, carry: 1 }),
|
|
|
|
#[test_case(0x93, 0xF0, 0x0F, register::SingleEightBit::E, AdditionOperationFlags { zero: 0, half_carry: 1, carry: 0 }; "half carry from E")]
|
|
|
|
(0x01, 0x01, AdditionOperationFlags{ zero: 1, half_carry: 0, carry: 0 })
|
|
|
|
#[test_case(0x93, 0x0F, 0xF0, register::SingleEightBit::E, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 1 }; "full carry from E")]
|
|
|
|
]
|
|
|
|
#[test_case(0x93, 0x01, 0x01, register::SingleEightBit::E, AdditionOperationFlags { zero: 1, half_carry: 0, carry: 0 }; "zero from E")]
|
|
|
|
)]
|
|
|
|
#[test_case(0x94, 0xFF, 0x0F, register::SingleEightBit::H, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 0 }; "no flags from H")]
|
|
|
|
|
|
|
|
#[test_case(0x94, 0xF0, 0x0F, register::SingleEightBit::H, AdditionOperationFlags { zero: 0, half_carry: 1, carry: 0 }; "half carry from H")]
|
|
|
|
|
|
|
|
#[test_case(0x94, 0x0F, 0xF0, register::SingleEightBit::H, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 1 }; "full carry from H")]
|
|
|
|
|
|
|
|
#[test_case(0x94, 0x01, 0x01, register::SingleEightBit::H, AdditionOperationFlags { zero: 1, half_carry: 0, carry: 0 }; "zero from H")]
|
|
|
|
|
|
|
|
#[test_case(0x95, 0xFF, 0x0F, register::SingleEightBit::L, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 0 }; "no flags from L")]
|
|
|
|
|
|
|
|
#[test_case(0x95, 0xF0, 0x0F, register::SingleEightBit::L, AdditionOperationFlags { zero: 0, half_carry: 1, carry: 0 }; "half carry from L")]
|
|
|
|
|
|
|
|
#[test_case(0x95, 0x0F, 0xF0, register::SingleEightBit::L, AdditionOperationFlags { zero: 0, half_carry: 0, carry: 1 }; "full carry from L")]
|
|
|
|
|
|
|
|
#[test_case(0x95, 0x01, 0x01, register::SingleEightBit::L, AdditionOperationFlags { zero: 1, half_carry: 0, carry: 0 }; "zero from L")]
|
|
|
|
|
|
|
|
fn test_sub_register_from_a_flags(
|
|
|
|
fn test_sub_register_from_a_flags(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, expected_flags): (u8, u8, AdditionOperationFlags),
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
expected_flags: AdditionOperationFlags,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor.registers.a = a_value;
|
|
|
|
processor.registers.a = a_value;
|
|
|
|
@ -689,25 +652,23 @@ fn test_sub_a_from_itself() {
|
|
|
|
);
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0x98, 0xFF, 0x0F, 0, register::SingleEightBit::B, 0xF0; "subtract B with no carry")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x98, 0xFF, 0x0F, 1, register::SingleEightBit::B, 0xEF; "subtract B with carry")]
|
|
|
|
[
|
|
|
|
#[test_case(0x99, 0xFF, 0x0F, 0, register::SingleEightBit::C, 0xF0; "subtract C with no carry")]
|
|
|
|
(0x98, register::SingleEightBit::B),
|
|
|
|
#[test_case(0x99, 0xFF, 0x0F, 1, register::SingleEightBit::C, 0xEF; "subtract C with carry")]
|
|
|
|
(0x99, register::SingleEightBit::C),
|
|
|
|
#[test_case(0x9A, 0xFF, 0x0F, 0, register::SingleEightBit::D, 0xF0; "subtract D with no carry")]
|
|
|
|
(0x9A, register::SingleEightBit::D),
|
|
|
|
#[test_case(0x9A, 0xFF, 0x0F, 1, register::SingleEightBit::D, 0xEF; "subtract D with carry")]
|
|
|
|
(0x9B, register::SingleEightBit::E),
|
|
|
|
#[test_case(0x9B, 0xFF, 0x0F, 0, register::SingleEightBit::E, 0xF0; "subtract E with no carry")]
|
|
|
|
(0x9C, register::SingleEightBit::H),
|
|
|
|
#[test_case(0x9B, 0xFF, 0x0F, 1, register::SingleEightBit::E, 0xEF; "subtract E with carry")]
|
|
|
|
(0x9D, register::SingleEightBit::L),
|
|
|
|
#[test_case(0x9C, 0xFF, 0x0F, 0, register::SingleEightBit::H, 0xF0; "subtract H with no carry")]
|
|
|
|
],
|
|
|
|
#[test_case(0x9C, 0xFF, 0x0F, 1, register::SingleEightBit::H, 0xEF; "subtract H with carry")]
|
|
|
|
[
|
|
|
|
#[test_case(0x9D, 0xFF, 0x0F, 0, register::SingleEightBit::L, 0xF0; "subtract L with no carry")]
|
|
|
|
(0xFF, 0x0F, 0, 0xF0),
|
|
|
|
#[test_case(0x9D, 0xFF, 0x0F, 1, register::SingleEightBit::L, 0xEF; "subtract L with carry")]
|
|
|
|
(0xFF, 0x0F, 1, 0xEF)
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_sub_register_with_carry_from_a_value(
|
|
|
|
fn test_sub_register_with_carry_from_a_value(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, carry_bit, expected): (u8, u8, u8, u8),
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
carry_bit: u8,
|
|
|
|
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
expected: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor.registers.a = a_value;
|
|
|
|
processor.registers.a = a_value;
|
|
|
|
@ -727,74 +688,33 @@ fn test_sub_register_with_carry_from_a_value(
|
|
|
|
processor.run_instruction(&ins);
|
|
|
|
processor.run_instruction(&ins);
|
|
|
|
assert_eq!(processor.registers.a, expected);
|
|
|
|
assert_eq!(processor.registers.a, expected);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[test_matrix(
|
|
|
|
|
|
|
|
[
|
|
|
|
|
|
|
|
(0x98, register::SingleEightBit::B),
|
|
|
|
|
|
|
|
(0x99, register::SingleEightBit::C),
|
|
|
|
|
|
|
|
(0x9A, register::SingleEightBit::D),
|
|
|
|
|
|
|
|
(0x9B, register::SingleEightBit::E),
|
|
|
|
|
|
|
|
(0x9C, register::SingleEightBit::H),
|
|
|
|
|
|
|
|
(0x9D, register::SingleEightBit::L),
|
|
|
|
|
|
|
|
],
|
|
|
|
|
|
|
|
[
|
|
|
|
|
|
|
|
(0xFE, 0x01, 0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}),
|
|
|
|
|
|
|
|
(0xFE, 0x01, 1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}),
|
|
|
|
|
|
|
|
|
|
|
|
// Register B
|
|
|
|
(0x00, 0x00, 0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}),
|
|
|
|
#[test_case(0x98, 0xFE, 0, register::SingleEightBit::B, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register b")]
|
|
|
|
(0x01, 0x00, 1, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}),
|
|
|
|
#[test_case(0x98, 0xFE, 1, register::SingleEightBit::B, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register b")]
|
|
|
|
(0x02, 0x02, 0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}),
|
|
|
|
#[test_case(0x98, 0x00, 0, register::SingleEightBit::B, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "all zero operands give zero flag, register b")]
|
|
|
|
|
|
|
|
#[test_case(0x98, 0x01, 1, register::SingleEightBit::B, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 1 gives zero flag with carry bit, register b")]
|
|
|
|
(0xF0, 0x0F, 0, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
|
|
|
|
#[test_case(0x98, 0x02, 0, register::SingleEightBit::B, 0x2, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 2 gives zero flag with no, register b")]
|
|
|
|
(0x0F, 0xF0, 0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}),
|
|
|
|
#[test_case(0x98, 0xF0, 0, register::SingleEightBit::B, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit set, half carry bit, register b")]
|
|
|
|
|
|
|
|
#[test_case(0x98, 0x0F, 0, register::SingleEightBit::B, 0xF0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "no carry bit set, full carry bit, register b")]
|
|
|
|
(0xF0, 0x0E, 1, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}),
|
|
|
|
#[test_case(0x98, 0xF0, 1, register::SingleEightBit::B, 0x0E, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit set, half carry bit, register b")]
|
|
|
|
(0x0F, 0xEE, 1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}),
|
|
|
|
#[test_case(0x98, 0x0F, 1, register::SingleEightBit::B, 0xEE, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "carry bit set, full carry bit, register b")]
|
|
|
|
]
|
|
|
|
// Register C
|
|
|
|
)]
|
|
|
|
#[test_case(0x99, 0xFE, 0, register::SingleEightBit::C, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register c")]
|
|
|
|
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|
#[test_case(0x99, 0xFE, 1, register::SingleEightBit::C, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register c")]
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|
|
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|
#[test_case(0x99, 0x00, 0, register::SingleEightBit::C, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "all zero operands give zero flag, register c")]
|
|
|
|
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|
#[test_case(0x99, 0x01, 1, register::SingleEightBit::C, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 1 gives zero flag with carry bit, register c")]
|
|
|
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|
|
|
#[test_case(0x99, 0x02, 0, register::SingleEightBit::C, 0x2, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 2 gives zero flag with no, register c")]
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|
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|
#[test_case(0x99, 0xF0, 0, register::SingleEightBit::C, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit set, half carry bit, register c")]
|
|
|
|
|
|
|
|
#[test_case(0x99, 0x0F, 0, register::SingleEightBit::C, 0xF0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "no carry bit set, full carry bit, register c")]
|
|
|
|
|
|
|
|
#[test_case(0x99, 0xF0, 1, register::SingleEightBit::C, 0x0E, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit set, half carry bit, register c")]
|
|
|
|
|
|
|
|
#[test_case(0x99, 0x0F, 1, register::SingleEightBit::C, 0xEE, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "carry bit set, full carry bit, register c")]
|
|
|
|
|
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|
|
// Register D
|
|
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|
#[test_case(0x9A, 0xFE, 0, register::SingleEightBit::D, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0xFE, 1, register::SingleEightBit::D, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0x00, 0, register::SingleEightBit::D, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "all zero operands give zero flag, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0x01, 1, register::SingleEightBit::D, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 1 gives zero flag with carry bit, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0x02, 0, register::SingleEightBit::D, 0x2, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 2 gives zero flag with no, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0xF0, 0, register::SingleEightBit::D, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit set, half carry bit, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0x0F, 0, register::SingleEightBit::D, 0xF0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "no carry bit set, full carry bit, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0xF0, 1, register::SingleEightBit::D, 0x0E, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit set, half carry bit, register d")]
|
|
|
|
|
|
|
|
#[test_case(0x9A, 0x0F, 1, register::SingleEightBit::D, 0xEE, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "carry bit set, full carry bit, register d")]
|
|
|
|
|
|
|
|
// Register E
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0xFE, 0, register::SingleEightBit::E, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0xFE, 1, register::SingleEightBit::E, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0x00, 0, register::SingleEightBit::E, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "all zero operands give zero flag, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0x01, 1, register::SingleEightBit::E, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 1 gives zero flag with carry bit, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0x02, 0, register::SingleEightBit::E, 0x2, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 2 gives zero flag with no, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0xF0, 0, register::SingleEightBit::E, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit set, half carry bit, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0x0F, 0, register::SingleEightBit::E, 0xF0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "no carry bit set, full carry bit, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0xF0, 1, register::SingleEightBit::E, 0x0E, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit set, half carry bit, register e")]
|
|
|
|
|
|
|
|
#[test_case(0x9B, 0x0F, 1, register::SingleEightBit::E, 0xEE, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "carry bit set, full carry bit, register e")]
|
|
|
|
|
|
|
|
// Register H
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0xFE, 0, register::SingleEightBit::H, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0xFE, 1, register::SingleEightBit::H, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0x00, 0, register::SingleEightBit::H, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "all zero operands give zero flag, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0x01, 1, register::SingleEightBit::H, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 1 gives zero flag with carry bit, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0x02, 0, register::SingleEightBit::H, 0x2, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 2 gives zero flag with no, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0xF0, 0, register::SingleEightBit::H, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit set, half carry bit, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0x0F, 0, register::SingleEightBit::H, 0xF0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "no carry bit set, full carry bit, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0xF0, 1, register::SingleEightBit::H, 0x0E, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit set, half carry bit, register h")]
|
|
|
|
|
|
|
|
#[test_case(0x9C, 0x0F, 1, register::SingleEightBit::H, 0xEE, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "carry bit set, full carry bit, register h")]
|
|
|
|
|
|
|
|
// Register L
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0xFE, 0, register::SingleEightBit::L, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "no carry bit set, results in no flags, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0xFE, 1, register::SingleEightBit::L, 0x1, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 0}; "carry bit set, results in no flags, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0x00, 0, register::SingleEightBit::L, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "all zero operands give zero flag, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0x01, 1, register::SingleEightBit::L, 0x0, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 1 gives zero flag with carry bit, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0x02, 0, register::SingleEightBit::L, 0x2, AdditionOperationFlags{zero: 1, half_carry: 0, carry: 0}; "subtracting from 2 gives zero flag with no, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0xF0, 0, register::SingleEightBit::L, 0x0F, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "no carry bit set, half carry bit, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0x0F, 0, register::SingleEightBit::L, 0xF0, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "no carry bit set, full carry bit, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0xF0, 1, register::SingleEightBit::L, 0x0E, AdditionOperationFlags{zero: 0, half_carry: 1, carry: 0}; "carry bit set, half carry bit, register l")]
|
|
|
|
|
|
|
|
#[test_case(0x9D, 0x0F, 1, register::SingleEightBit::L, 0xEE, AdditionOperationFlags{zero: 0, half_carry: 0, carry: 1}; "carry bit set, full carry bit, register l")]
|
|
|
|
|
|
|
|
fn test_sub_register_from_carry_from_a_flags(
|
|
|
|
fn test_sub_register_from_carry_from_a_flags(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
initial_value: u8,
|
|
|
|
(initial_value, operand, carry_bit, expected_flags): (u8, u8, u8, AdditionOperationFlags),
|
|
|
|
carry_bit: u8,
|
|
|
|
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
expected_flags: AdditionOperationFlags,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor.registers.a = initial_value;
|
|
|
|
processor.registers.a = initial_value;
|
|
|
|
@ -1191,20 +1111,21 @@ fn test_and_single_register_with_a_value(
|
|
|
|
assert_eq!(expected_value, processor.registers.a);
|
|
|
|
assert_eq!(expected_value, processor.registers.a);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0xA0, 0xFA, register::SingleEightBit::B, 0x0F, 0; "AND with B, not zero")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0xA0, 0xFA, register::SingleEightBit::B, 0x00, 1; "AND with B, zero")]
|
|
|
|
[
|
|
|
|
#[test_case(0xA1, 0xFA, register::SingleEightBit::C, 0x0F, 0; "AND with C, not zero")]
|
|
|
|
(0xA0, register::SingleEightBit::B),
|
|
|
|
#[test_case(0xA1, 0xFA, register::SingleEightBit::C, 0x00, 1; "AND with C, zero")]
|
|
|
|
(0xA1, register::SingleEightBit::C),
|
|
|
|
#[test_case(0xA2, 0xFA, register::SingleEightBit::D, 0x0F, 0; "AND with D, not zero")]
|
|
|
|
(0xA2, register::SingleEightBit::D),
|
|
|
|
#[test_case(0xA2, 0xFA, register::SingleEightBit::D, 0x00, 1; "AND with D, zero")]
|
|
|
|
(0xA3, register::SingleEightBit::E),
|
|
|
|
#[test_case(0xA3, 0xFA, register::SingleEightBit::E, 0x0F, 0; "AND with E, not zero")]
|
|
|
|
],
|
|
|
|
#[test_case(0xA3, 0xFA, register::SingleEightBit::E, 0x00, 1; "AND with E, zero")]
|
|
|
|
[
|
|
|
|
|
|
|
|
(0xFA, 0x0F, 0),
|
|
|
|
|
|
|
|
(0xFA, 0x00, 1),
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_and_single_register_with_a_flags(
|
|
|
|
fn test_and_single_register_with_a_flags(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, expected_zero_flag): (u8, u8, u8),
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
expected_zero_flag: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
// Set all the register to the opposite we expect to ensure they all get set
|
|
|
|
// Set all the register to the opposite we expect to ensure they all get set
|
|
|
|
@ -1357,12 +1278,12 @@ fn test_and_immediate_with_a_flags(a_value: u8, operand: u8, expected_zero_flag:
|
|
|
|
);
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0xA8, 0xFF, register::SingleEightBit::B, 0xCC, 0x33; "register b")]
|
|
|
|
#[test_case(0xA8, 0xFF, register::SingleEightBit::B, 0xCC, 0x33; "register B")]
|
|
|
|
#[test_case(0xA9, 0xFF, register::SingleEightBit::C, 0x33, 0xCC; "register c")]
|
|
|
|
#[test_case(0xA9, 0xFF, register::SingleEightBit::C, 0x33, 0xCC; "register C")]
|
|
|
|
#[test_case(0xAA, 0xFF, register::SingleEightBit::D, 0xCC, 0x33; "register d")]
|
|
|
|
#[test_case(0xAA, 0xFF, register::SingleEightBit::D, 0xCC, 0x33; "register D")]
|
|
|
|
#[test_case(0xAB, 0xFF, register::SingleEightBit::E, 0x33, 0xCC; "register e")]
|
|
|
|
#[test_case(0xAB, 0xFF, register::SingleEightBit::E, 0x33, 0xCC; "register E")]
|
|
|
|
#[test_case(0xAC, 0xFF, register::SingleEightBit::H, 0xCC, 0x33; "register h")]
|
|
|
|
#[test_case(0xAC, 0xFF, register::SingleEightBit::H, 0xCC, 0x33; "register H")]
|
|
|
|
#[test_case(0xAD, 0xFF, register::SingleEightBit::L, 0x33, 0xCC; "register l")]
|
|
|
|
#[test_case(0xAD, 0xFF, register::SingleEightBit::L, 0x33, 0xCC; "register L")]
|
|
|
|
fn test_xor_register_with_a_value(
|
|
|
|
fn test_xor_register_with_a_value(
|
|
|
|
opcode: u8,
|
|
|
|
opcode: u8,
|
|
|
|
a_value: u8,
|
|
|
|
a_value: u8,
|
|
|
|
@ -1387,24 +1308,23 @@ fn test_xor_register_with_a_value(
|
|
|
|
assert_eq!(expected_value, processor.registers.a);
|
|
|
|
assert_eq!(expected_value, processor.registers.a);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0xA8, 0xFF, register::SingleEightBit::B, 0xCC, 0; "register b, not zero")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0xA8, 0xCC, register::SingleEightBit::B, 0xCC, 1; "register b, zero")]
|
|
|
|
[
|
|
|
|
#[test_case(0xA9, 0xFF, register::SingleEightBit::C, 0x33, 0; "register c, not zero")]
|
|
|
|
(0xA8, register::SingleEightBit::B),
|
|
|
|
#[test_case(0xA9, 0x33, register::SingleEightBit::C, 0x33, 1; "register c, zero")]
|
|
|
|
(0xA9, register::SingleEightBit::C),
|
|
|
|
#[test_case(0xAA, 0xFF, register::SingleEightBit::D, 0xCC, 0; "register d, not zero")]
|
|
|
|
(0xAA, register::SingleEightBit::D),
|
|
|
|
#[test_case(0xAA, 0xCC, register::SingleEightBit::D, 0xCC, 1; "register d, zero")]
|
|
|
|
(0xAB, register::SingleEightBit::E),
|
|
|
|
#[test_case(0xAB, 0xFF, register::SingleEightBit::E, 0x33, 0; "register e, not zero")]
|
|
|
|
(0xAC, register::SingleEightBit::H),
|
|
|
|
#[test_case(0xAB, 0x33, register::SingleEightBit::E, 0x33, 1; "register e, zero")]
|
|
|
|
(0xAD, register::SingleEightBit::L),
|
|
|
|
#[test_case(0xAC, 0xFF, register::SingleEightBit::H, 0xCC, 0; "register h, not zero")]
|
|
|
|
],
|
|
|
|
#[test_case(0xAC, 0xCC, register::SingleEightBit::H, 0xCC, 1; "register h, zero")]
|
|
|
|
[
|
|
|
|
#[test_case(0xAD, 0xFF, register::SingleEightBit::L, 0x33, 0; "register l, not zero")]
|
|
|
|
(0xFF, 0xCC, 0),
|
|
|
|
#[test_case(0xAD, 0x33, register::SingleEightBit::L, 0x33, 1; "register l, zero")]
|
|
|
|
(0xCC, 0xCC, 1),
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_xor_register_with_a_flags(
|
|
|
|
fn test_xor_register_with_a_flags(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, expected_zero_flag): (u8, u8, u8),
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
expected_zero_flag: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
// Set all the register to the opposite we expect to ensure they all get set
|
|
|
|
// Set all the register to the opposite we expect to ensure they all get set
|
|
|
|
@ -1562,18 +1482,23 @@ fn test_xor_immediate_value_with_a_flags(a_value: u8, operand: u8, expected_zero
|
|
|
|
);
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0xB0, 0xCC, register::SingleEightBit::B, 0x11, 0xDD; "register b")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0xB1, 0xCC, register::SingleEightBit::C, 0x11, 0xDD; "register c")]
|
|
|
|
[
|
|
|
|
#[test_case(0xB2, 0xCC, register::SingleEightBit::D, 0x11, 0xDD; "register d")]
|
|
|
|
(0xB0, register::SingleEightBit:: B),
|
|
|
|
#[test_case(0xB3, 0xCC, register::SingleEightBit::E, 0x11, 0xDD; "register e")]
|
|
|
|
(0xB1, register::SingleEightBit:: C),
|
|
|
|
#[test_case(0xB4, 0xCC, register::SingleEightBit::H, 0x11, 0xDD; "register h")]
|
|
|
|
(0xB2, register::SingleEightBit:: D),
|
|
|
|
#[test_case(0xB5, 0xCC, register::SingleEightBit::L, 0x11, 0xDD; "register l")]
|
|
|
|
(0xB3, register::SingleEightBit:: E),
|
|
|
|
|
|
|
|
(0xB4, register::SingleEightBit:: H),
|
|
|
|
|
|
|
|
(0xB5, register::SingleEightBit:: L),
|
|
|
|
|
|
|
|
],
|
|
|
|
|
|
|
|
[
|
|
|
|
|
|
|
|
(0xCC, 0x11, 0xDD),
|
|
|
|
|
|
|
|
(0x00, 0x1F, 0x1F)
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_or_register_with_a_value(
|
|
|
|
fn test_or_register_with_a_value(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, expected_value): (u8, u8, u8),
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
expected_value: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor
|
|
|
|
processor
|
|
|
|
@ -1592,24 +1517,23 @@ fn test_or_register_with_a_value(
|
|
|
|
assert_eq!(expected_value, processor.registers.a);
|
|
|
|
assert_eq!(expected_value, processor.registers.a);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0xB0, 0xCC, register::SingleEightBit::B, 0x22, 0; "register b, not zero")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0xB0, 0x00, register::SingleEightBit::B, 0x00, 1; "register b, zero")]
|
|
|
|
[
|
|
|
|
#[test_case(0xB1, 0xCC, register::SingleEightBit::C, 0x22, 0; "register c, not zero")]
|
|
|
|
(0xB0, register::SingleEightBit::B),
|
|
|
|
#[test_case(0xB1, 0x00, register::SingleEightBit::C, 0x00, 1; "register c, zero")]
|
|
|
|
(0xB1, register::SingleEightBit::C),
|
|
|
|
#[test_case(0xB2, 0xCC, register::SingleEightBit::D, 0x22, 0; "register d, not zero")]
|
|
|
|
(0xB2, register::SingleEightBit::D),
|
|
|
|
#[test_case(0xB2, 0x00, register::SingleEightBit::D, 0x00, 1; "register d, zero")]
|
|
|
|
(0xB3, register::SingleEightBit::E),
|
|
|
|
#[test_case(0xB3, 0xCC, register::SingleEightBit::E, 0x22, 0; "register e, not zero")]
|
|
|
|
(0xB4, register::SingleEightBit::H),
|
|
|
|
#[test_case(0xB3, 0x00, register::SingleEightBit::E, 0x00, 1; "register e, zero")]
|
|
|
|
(0xB5, register::SingleEightBit::L),
|
|
|
|
#[test_case(0xB4, 0xCC, register::SingleEightBit::H, 0x22, 0; "register h, not zero")]
|
|
|
|
],
|
|
|
|
#[test_case(0xB4, 0x00, register::SingleEightBit::H, 0x00, 1; "register h, zero")]
|
|
|
|
[
|
|
|
|
#[test_case(0xB5, 0xCC, register::SingleEightBit::L, 0x22, 0; "register l, not zero")]
|
|
|
|
(0xCC, 0x22, 0),
|
|
|
|
#[test_case(0xB5, 0x00, register::SingleEightBit::L, 0x00, 1; "register l, zero")]
|
|
|
|
(0x00, 0x00, 1),
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_or_register_with_a_flags(
|
|
|
|
fn test_or_register_with_a_flags(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, operand_register): (u8, register::SingleEightBit),
|
|
|
|
a_value: u8,
|
|
|
|
(a_value, operand, expected_zero_flag): (u8, u8, u8),
|
|
|
|
operand_register: register::SingleEightBit,
|
|
|
|
|
|
|
|
operand: u8,
|
|
|
|
|
|
|
|
expected_zero_flag: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
// Set all the register to the opposite we expect to ensure they all get set
|
|
|
|
// Set all the register to the opposite we expect to ensure they all get set
|
|
|
|
@ -2136,40 +2060,41 @@ fn test_comparing_immediate_value_to_a(
|
|
|
|
);
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0x04, register::SingleEightBit::B, 0x05, 0x06; "add one, register B")]
|
|
|
|
// increment
|
|
|
|
#[test_case(0x04, register::SingleEightBit::B, 0xFF, 0x00; "add one with wrapping, register B")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x0C, register::SingleEightBit::C, 0x05, 0x06; "add one, register C")]
|
|
|
|
[
|
|
|
|
#[test_case(0x0C, register::SingleEightBit::C, 0xFF, 0x00; "add one with wrapping, register C")]
|
|
|
|
(0x04, register::SingleEightBit:: B),
|
|
|
|
#[test_case(0x14, register::SingleEightBit::D, 0x05, 0x06; "add one, register D")]
|
|
|
|
(0x0C, register::SingleEightBit:: C),
|
|
|
|
#[test_case(0x14, register::SingleEightBit::D, 0xFF, 0x00; "add one with wrapping, register D")]
|
|
|
|
(0x14, register::SingleEightBit:: D),
|
|
|
|
#[test_case(0x1C, register::SingleEightBit::E, 0x05, 0x06; "add one, register E")]
|
|
|
|
(0x1C, register::SingleEightBit:: E),
|
|
|
|
#[test_case(0x1C, register::SingleEightBit::E, 0xFF, 0x00; "add one with wrapping, register E")]
|
|
|
|
(0x24, register::SingleEightBit:: H),
|
|
|
|
#[test_case(0x24, register::SingleEightBit::H, 0x05, 0x06; "add one, register H")]
|
|
|
|
(0x2C, register::SingleEightBit:: L),
|
|
|
|
#[test_case(0x24, register::SingleEightBit::H, 0xFF, 0x00; "add one with wrapping, register H")]
|
|
|
|
(0x3C, register::SingleEightBit:: A),
|
|
|
|
#[test_case(0x2C, register::SingleEightBit::L, 0x05, 0x06; "add one, register L")]
|
|
|
|
],
|
|
|
|
#[test_case(0x2C, register::SingleEightBit::L, 0xFF, 0x00; "add one with wrapping, register L")]
|
|
|
|
[
|
|
|
|
#[test_case(0x3C, register::SingleEightBit::A, 0x05, 0x06; "add one, register A")]
|
|
|
|
(0x05, 0x06),
|
|
|
|
#[test_case(0x3C, register::SingleEightBit::A, 0xFF, 0x00; "add one with wrapping, register A")]
|
|
|
|
(0xFF, 0x00),
|
|
|
|
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
// decrement
|
|
|
|
// decrement
|
|
|
|
#[test_case(0x05, register::SingleEightBit::B, 0x05, 0x04; "sub one, register B")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x05, register::SingleEightBit::B, 0x00, 0xFF; "sub one with wrapping, register B")]
|
|
|
|
[
|
|
|
|
#[test_case(0x0D, register::SingleEightBit::C, 0x05, 0x04; "sub one, register C")]
|
|
|
|
(0x05, register::SingleEightBit:: B),
|
|
|
|
#[test_case(0x0D, register::SingleEightBit::C, 0x00, 0xFF; "sub one with wrapping, register C")]
|
|
|
|
(0x0D, register::SingleEightBit:: C),
|
|
|
|
#[test_case(0x15, register::SingleEightBit::D, 0x05, 0x04; "sub one, register D")]
|
|
|
|
(0x15, register::SingleEightBit:: D),
|
|
|
|
#[test_case(0x15, register::SingleEightBit::D, 0x00, 0xFF; "sub one with wrapping, register D")]
|
|
|
|
(0x1D, register::SingleEightBit:: E),
|
|
|
|
#[test_case(0x1D, register::SingleEightBit::E, 0x05, 0x04; "sub one, register E")]
|
|
|
|
(0x25, register::SingleEightBit:: H),
|
|
|
|
#[test_case(0x1D, register::SingleEightBit::E, 0x00, 0xFF; "sub one with wrapping, register E")]
|
|
|
|
(0x2D, register::SingleEightBit:: L),
|
|
|
|
#[test_case(0x25, register::SingleEightBit::H, 0x05, 0x04; "sub one, register H")]
|
|
|
|
(0x3D, register::SingleEightBit:: A),
|
|
|
|
#[test_case(0x25, register::SingleEightBit::H, 0x00, 0xFF; "sub one with wrapping, register H")]
|
|
|
|
],
|
|
|
|
#[test_case(0x2D, register::SingleEightBit::L, 0x05, 0x04; "sub one, register L")]
|
|
|
|
[
|
|
|
|
#[test_case(0x2D, register::SingleEightBit::L, 0x00, 0xFF; "sub one with wrapping, register L")]
|
|
|
|
(0x05, 0x04),
|
|
|
|
#[test_case(0x3D, register::SingleEightBit::A, 0x05, 0x04; "sub one, register A")]
|
|
|
|
(0x00, 0xFF),
|
|
|
|
#[test_case(0x3D, register::SingleEightBit::A, 0x00, 0xFF; "sub one with wrapping, register A")]
|
|
|
|
]
|
|
|
|
|
|
|
|
)]
|
|
|
|
fn test_increment_decrement_single_register_value(
|
|
|
|
fn test_increment_decrement_single_register_value(
|
|
|
|
opcode: u8,
|
|
|
|
(opcode, register): (u8, register::SingleEightBit),
|
|
|
|
register: register::SingleEightBit,
|
|
|
|
(initial_value, expected_value): (u8, u8),
|
|
|
|
initial_value: u8,
|
|
|
|
|
|
|
|
expected_value: u8,
|
|
|
|
|
|
|
|
) {
|
|
|
|
) {
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
let mut processor = Processor::default();
|
|
|
|
processor
|
|
|
|
processor
|
|
|
|
@ -2188,61 +2113,42 @@ fn test_increment_decrement_single_register_value(
|
|
|
|
);
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#[test_case(0x04, register::SingleEightBit::B, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0}; "increment, register B")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x04, register::SingleEightBit::B, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0}; "increment with wrapping, register B")]
|
|
|
|
[
|
|
|
|
#[test_case(0x04, register::SingleEightBit::B, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register B")]
|
|
|
|
(0x04, register::SingleEightBit::B),
|
|
|
|
#[test_case(0x0C, register::SingleEightBit::C, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register C")]
|
|
|
|
(0x0C, register::SingleEightBit::C),
|
|
|
|
#[test_case(0x0C, register::SingleEightBit::C, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register C")]
|
|
|
|
(0x14, register::SingleEightBit::D),
|
|
|
|
#[test_case(0x0C, register::SingleEightBit::C, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register C")]
|
|
|
|
(0x1C, register::SingleEightBit::E),
|
|
|
|
#[test_case(0x14, register::SingleEightBit::D, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register D")]
|
|
|
|
(0x24, register::SingleEightBit::H),
|
|
|
|
#[test_case(0x14, register::SingleEightBit::D, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register D")]
|
|
|
|
(0x2C, register::SingleEightBit::L),
|
|
|
|
#[test_case(0x14, register::SingleEightBit::D, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register D")]
|
|
|
|
(0x3C, register::SingleEightBit::A),
|
|
|
|
#[test_case(0x1C, register::SingleEightBit::E, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register E")]
|
|
|
|
],
|
|
|
|
#[test_case(0x1C, register::SingleEightBit::E, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register E")]
|
|
|
|
[
|
|
|
|
#[test_case(0x1C, register::SingleEightBit::E, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register E")]
|
|
|
|
(0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0}),
|
|
|
|
#[test_case(0x24, register::SingleEightBit::H, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register H")]
|
|
|
|
(0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0}),
|
|
|
|
#[test_case(0x24, register::SingleEightBit::H, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register H")]
|
|
|
|
(0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0}),
|
|
|
|
#[test_case(0x24, register::SingleEightBit::H, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register H")]
|
|
|
|
]
|
|
|
|
#[test_case(0x2C, register::SingleEightBit::L, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register L")]
|
|
|
|
)]
|
|
|
|
#[test_case(0x2C, register::SingleEightBit::L, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register L")]
|
|
|
|
#[test_matrix(
|
|
|
|
#[test_case(0x2C, register::SingleEightBit::L, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register L")]
|
|
|
|
[
|
|
|
|
#[test_case(0x3C, register::SingleEightBit::A, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register A")]
|
|
|
|
(0x05, register::SingleEightBit::B),
|
|
|
|
#[test_case(0x3C, register::SingleEightBit::A, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register A")]
|
|
|
|
(0x0D, register::SingleEightBit::C),
|
|
|
|
#[test_case(0x3C, register::SingleEightBit::A, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register A")]
|
|
|
|
(0x15, register::SingleEightBit::D),
|
|
|
|
// decrement
|
|
|
|
(0x1D, register::SingleEightBit::E),
|
|
|
|
#[test_case(0x05, register::SingleEightBit::B, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register B")]
|
|
|
|
(0x25, register::SingleEightBit::H),
|
|
|
|
#[test_case(0x05, register::SingleEightBit::B, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register B")]
|
|
|
|
(0x2D, register::SingleEightBit::L),
|
|
|
|
#[test_case(0x05, register::SingleEightBit::B, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register B")]
|
|
|
|
(0x3D, register::SingleEightBit::A),
|
|
|
|
#[test_case(0x05, register::SingleEightBit::B, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register B")]
|
|
|
|
],
|
|
|
|
#[test_case(0x0D, register::SingleEightBit::C, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register C")]
|
|
|
|
[
|
|
|
|
#[test_case(0x0D, register::SingleEightBit::C, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register C")]
|
|
|
|
(0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}),
|
|
|
|
#[test_case(0x0D, register::SingleEightBit::C, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register C")]
|
|
|
|
(0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}),
|
|
|
|
#[test_case(0x0D, register::SingleEightBit::C, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register C")]
|
|
|
|
(0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}),
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#[test_case(0x15, register::SingleEightBit::D, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register D")]
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(0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}),
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#[test_case(0x15, register::SingleEightBit::D, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register D")]
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]
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#[test_case(0x15, register::SingleEightBit::D, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register D")]
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)]
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#[test_case(0x15, register::SingleEightBit::D, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register D")]
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#[test_case(0x1D, register::SingleEightBit::E, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register E")]
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#[test_case(0x1D, register::SingleEightBit::E, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register E")]
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#[test_case(0x1D, register::SingleEightBit::E, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register E")]
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#[test_case(0x1D, register::SingleEightBit::E, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register E")]
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#[test_case(0x25, register::SingleEightBit::H, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register H")]
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#[test_case(0x25, register::SingleEightBit::H, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register H")]
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#[test_case(0x25, register::SingleEightBit::H, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register H")]
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#[test_case(0x25, register::SingleEightBit::H, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register H")]
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#[test_case(0x2D, register::SingleEightBit::L, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register L")]
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#[test_case(0x2D, register::SingleEightBit::L, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register L")]
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#[test_case(0x2D, register::SingleEightBit::L, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register L")]
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#[test_case(0x2D, register::SingleEightBit::L, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register L")]
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#[test_case(0x3D, register::SingleEightBit::A, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register A")]
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#[test_case(0x3D, register::SingleEightBit::A, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register A")]
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#[test_case(0x3D, register::SingleEightBit::A, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register A")]
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#[test_case(0x3D, register::SingleEightBit::A, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register A")]
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fn test_increment_decrement_single_register_flags(
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fn test_increment_decrement_single_register_flags(
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opcode: u8,
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(opcode, register): (u8, register::SingleEightBit),
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register: register::SingleEightBit,
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(initial_value, expected_flags): (u8, IncrementOperationFlags),
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initial_value: u8,
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expected_flags: IncrementOperationFlags,
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) {
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) {
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let mut processor = Processor::default();
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let mut processor = Processor::default();
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processor
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processor
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@ -2313,7 +2219,11 @@ fn test_increment_decrement_hl_value(opcode: u8, initial_value: u8, expected_val
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#[test_case(0x35, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero")]
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#[test_case(0x35, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero")]
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#[test_case(0x35, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping")]
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#[test_case(0x35, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping")]
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#[test_case(0x35, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry")]
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#[test_case(0x35, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry")]
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fn test_increment_decrement_hl_flags(opcode: u8, initial_value: u8, expected_flags: IncrementOperationFlags) {
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fn test_increment_decrement_hl_flags(
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opcode: u8,
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initial_value: u8,
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expected_flags: IncrementOperationFlags,
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) {
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let mut processor = Processor::default();
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let mut processor = Processor::default();
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processor
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processor
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.registers
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.registers
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