From 915f33307e76eb69ee88626ec802273ac7bace09 Mon Sep 17 00:00:00 2001 From: Nick Krichevsky Date: Sat, 17 Jun 2023 14:24:21 -0400 Subject: [PATCH] add support for dec instructions --- src/cpu/instructions/arith8.rs | 1 + src/cpu/parse.rs | 1 + src/cpu/parse/arith8.rs | 1 + src/cpu/parse/arith8/dec.rs | 37 ++++++ src/cpu/run/arith8.rs | 2 + src/cpu/run/arith8/unary.rs | 19 ++- tests/cpu/arith8.rs | 123 +++++++++++++----- .../cpu/jsmoo/testdata/{disabled => }/05.json | 0 .../cpu/jsmoo/testdata/{disabled => }/0d.json | 0 .../cpu/jsmoo/testdata/{disabled => }/15.json | 0 .../cpu/jsmoo/testdata/{disabled => }/1d.json | 0 .../cpu/jsmoo/testdata/{disabled => }/25.json | 0 .../cpu/jsmoo/testdata/{disabled => }/2d.json | 0 .../cpu/jsmoo/testdata/{disabled => }/35.json | 0 .../cpu/jsmoo/testdata/{disabled => }/3d.json | 0 15 files changed, 147 insertions(+), 37 deletions(-) create mode 100644 src/cpu/parse/arith8/dec.rs rename tests/cpu/jsmoo/testdata/{disabled => }/05.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/0d.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/15.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/1d.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/25.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/2d.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/35.json (100%) rename tests/cpu/jsmoo/testdata/{disabled => }/3d.json (100%) diff --git a/src/cpu/instructions/arith8.rs b/src/cpu/instructions/arith8.rs index 8e8b4dc..a0ddb1e 100644 --- a/src/cpu/instructions/arith8.rs +++ b/src/cpu/instructions/arith8.rs @@ -12,6 +12,7 @@ pub enum Operation { Or, Compare, Inc, + Dec, } #[derive(Debug, Copy, Clone)] diff --git a/src/cpu/parse.rs b/src/cpu/parse.rs index 5a37f71..1b50907 100644 --- a/src/cpu/parse.rs +++ b/src/cpu/parse.rs @@ -48,6 +48,7 @@ pub fn next_instruction(data: &View) -> ParseResult { arith8::or::Parser::parse_opcode, arith8::compare::Parser::parse_opcode, arith8::inc::Parser::parse_opcode, + arith8::dec::Parser::parse_opcode, ]; for parse_func in parse_funcs { diff --git a/src/cpu/parse/arith8.rs b/src/cpu/parse/arith8.rs index 22c6d1b..59628b0 100644 --- a/src/cpu/parse/arith8.rs +++ b/src/cpu/parse/arith8.rs @@ -12,6 +12,7 @@ use super::ParseOutput; pub mod add; pub mod and; pub mod compare; +pub mod dec; pub mod inc; pub mod or; pub mod sub; diff --git a/src/cpu/parse/arith8/dec.rs b/src/cpu/parse/arith8/dec.rs new file mode 100644 index 0000000..4cb81b5 --- /dev/null +++ b/src/cpu/parse/arith8/dec.rs @@ -0,0 +1,37 @@ +use crate::{ + cpu::{ + instructions::arith8::Operation, + parse::{self, Error, OpcodeParser, ParseOutput, ParseResult}, + }, + memory::View, + register, +}; + +pub struct Parser; + +impl OpcodeParser for Parser { + fn parse_opcode(data: &View) -> ParseResult { + let opcode = parse::get_opcode_from_data(data); + match opcode { + 0x05 => Ok(build_dec_single_register_data(register::SingleEightBit::B)), + 0x0D => Ok(build_dec_single_register_data(register::SingleEightBit::C)), + 0x15 => Ok(build_dec_single_register_data(register::SingleEightBit::D)), + 0x1D => Ok(build_dec_single_register_data(register::SingleEightBit::E)), + 0x25 => Ok(build_dec_single_register_data(register::SingleEightBit::H)), + 0x2D => Ok(build_dec_single_register_data(register::SingleEightBit::L)), + 0x3D => Ok(build_dec_single_register_data(register::SingleEightBit::A)), + + 0x35 => Ok(build_dec_hl_value_data()), + + _ => Err(Error::UnknownOpcode(opcode)), + } + } +} + +fn build_dec_single_register_data(src: register::SingleEightBit) -> ParseOutput { + super::build_instruction_between_register_and_a_data(Operation::Dec, src) +} + +fn build_dec_hl_value_data() -> ParseOutput { + super::build_instruction_between_hl_value_and_a_data(Operation::Dec) +} diff --git a/src/cpu/run/arith8.rs b/src/cpu/run/arith8.rs index 04b6666..89b4fc0 100644 --- a/src/cpu/run/arith8.rs +++ b/src/cpu/run/arith8.rs @@ -48,6 +48,8 @@ impl InstructionRunner for EightBitArithmeticRunn Operation::Compare => binary::run_compare(processor, instruction.operand), Operation::Inc => unary::run_inc(processor, instruction.operand), + + Operation::Dec => unary::run_dec(processor, instruction.operand), } } } diff --git a/src/cpu/run/arith8/unary.rs b/src/cpu/run/arith8/unary.rs index a2014b0..c0b2a20 100644 --- a/src/cpu/run/arith8/unary.rs +++ b/src/cpu/run/arith8/unary.rs @@ -1,7 +1,7 @@ use crate::{ cpu::{ instructions::arith8::Operand, - run::{arithutil::CarryingAdd, Error}, + run::{arithutil::{CarryingAdd, CarryingSub}, Error}, Processor, }, memory, register, @@ -26,6 +26,23 @@ pub fn run_inc(processor: &mut Processor, operand: Operand) -> Result<(), Error> }) } +pub fn run_dec(processor: &mut Processor, operand: Operand) -> Result<(), Error> { + let current_carry_flag = processor.registers.get_flag_bit(register::Flag::Carry); + run_operation(processor, operand, |value| { + let (result, half_carry, _full_carry) = value.sub_with_carry(1); + + OperationOutput { + value: result, + flags: OperationFlagOutput { + zero_flag: (result == 0).into(), + half_carry_flag: half_carry.into(), + carry_flag: current_carry_flag, + subtract_flag: 1, + }, + } + }) +} + fn run_operation(processor: &mut Processor, operand: Operand, operation: F) -> Result<(), Error> where F: Fn(u8) -> OperationOutput, diff --git a/tests/cpu/arith8.rs b/tests/cpu/arith8.rs index 4fc7c22..46f3d02 100644 --- a/tests/cpu/arith8.rs +++ b/tests/cpu/arith8.rs @@ -15,6 +15,7 @@ struct AdditionOperationFlags { struct IncrementOperationFlags { zero: u8, + subtract: u8, half_carry: u8, } @@ -2149,7 +2150,22 @@ fn test_comparing_immediate_value_to_a( #[test_case(0x2C, register::SingleEightBit::L, 0xFF, 0x00; "add one with wrapping, register L")] #[test_case(0x3C, register::SingleEightBit::A, 0x05, 0x06; "add one, register A")] #[test_case(0x3C, register::SingleEightBit::A, 0xFF, 0x00; "add one with wrapping, register A")] -fn test_increment_single_register_value( +// decrement +#[test_case(0x05, register::SingleEightBit::B, 0x05, 0x04; "sub one, register B")] +#[test_case(0x05, register::SingleEightBit::B, 0x00, 0xFF; "sub one with wrapping, register B")] +#[test_case(0x0D, register::SingleEightBit::C, 0x05, 0x04; "sub one, register C")] +#[test_case(0x0D, register::SingleEightBit::C, 0x00, 0xFF; "sub one with wrapping, register C")] +#[test_case(0x15, register::SingleEightBit::D, 0x05, 0x04; "sub one, register D")] +#[test_case(0x15, register::SingleEightBit::D, 0x00, 0xFF; "sub one with wrapping, register D")] +#[test_case(0x1D, register::SingleEightBit::E, 0x05, 0x04; "sub one, register E")] +#[test_case(0x1D, register::SingleEightBit::E, 0x00, 0xFF; "sub one with wrapping, register E")] +#[test_case(0x25, register::SingleEightBit::H, 0x05, 0x04; "sub one, register H")] +#[test_case(0x25, register::SingleEightBit::H, 0x00, 0xFF; "sub one with wrapping, register H")] +#[test_case(0x2D, register::SingleEightBit::L, 0x05, 0x04; "sub one, register L")] +#[test_case(0x2D, register::SingleEightBit::L, 0x00, 0xFF; "sub one with wrapping, register L")] +#[test_case(0x3D, register::SingleEightBit::A, 0x05, 0x04; "sub one, register A")] +#[test_case(0x3D, register::SingleEightBit::A, 0x00, 0xFF; "sub one with wrapping, register A")] +fn test_increment_decrement_single_register_value( opcode: u8, register: register::SingleEightBit, initial_value: u8, @@ -2172,28 +2188,57 @@ fn test_increment_single_register_value( ); } -#[test_case(0x04, register::SingleEightBit::B, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register B")] -#[test_case(0x04, register::SingleEightBit::B, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register B")] -#[test_case(0x04, register::SingleEightBit::B, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register B")] -#[test_case(0x0C, register::SingleEightBit::C, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register C")] -#[test_case(0x0C, register::SingleEightBit::C, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register C")] -#[test_case(0x0C, register::SingleEightBit::C, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register C")] -#[test_case(0x14, register::SingleEightBit::D, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register D")] -#[test_case(0x14, register::SingleEightBit::D, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register D")] -#[test_case(0x14, register::SingleEightBit::D, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register D")] -#[test_case(0x1C, register::SingleEightBit::E, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register E")] -#[test_case(0x1C, register::SingleEightBit::E, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register E")] -#[test_case(0x1C, register::SingleEightBit::E, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register E")] -#[test_case(0x24, register::SingleEightBit::H, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register H")] -#[test_case(0x24, register::SingleEightBit::H, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register H")] -#[test_case(0x24, register::SingleEightBit::H, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register H")] -#[test_case(0x2C, register::SingleEightBit::L, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register L")] -#[test_case(0x2C, register::SingleEightBit::L, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register L")] -#[test_case(0x2C, register::SingleEightBit::L, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register L")] -#[test_case(0x3C, register::SingleEightBit::A, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment, register A")] -#[test_case(0x3C, register::SingleEightBit::A, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping, register A")] -#[test_case(0x3C, register::SingleEightBit::A, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry, register A")] -fn test_increment_single_register_flags( +#[test_case(0x04, register::SingleEightBit::B, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0}; "increment, register B")] +#[test_case(0x04, register::SingleEightBit::B, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0}; "increment with wrapping, register B")] +#[test_case(0x04, register::SingleEightBit::B, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register B")] +#[test_case(0x0C, register::SingleEightBit::C, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register C")] +#[test_case(0x0C, register::SingleEightBit::C, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register C")] +#[test_case(0x0C, register::SingleEightBit::C, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register C")] +#[test_case(0x14, register::SingleEightBit::D, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register D")] +#[test_case(0x14, register::SingleEightBit::D, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register D")] +#[test_case(0x14, register::SingleEightBit::D, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register D")] +#[test_case(0x1C, register::SingleEightBit::E, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register E")] +#[test_case(0x1C, register::SingleEightBit::E, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register E")] +#[test_case(0x1C, register::SingleEightBit::E, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register E")] +#[test_case(0x24, register::SingleEightBit::H, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register H")] +#[test_case(0x24, register::SingleEightBit::H, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register H")] +#[test_case(0x24, register::SingleEightBit::H, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register H")] +#[test_case(0x2C, register::SingleEightBit::L, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register L")] +#[test_case(0x2C, register::SingleEightBit::L, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register L")] +#[test_case(0x2C, register::SingleEightBit::L, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register L")] +#[test_case(0x3C, register::SingleEightBit::A, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0 }; "increment, register A")] +#[test_case(0x3C, register::SingleEightBit::A, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0 }; "increment with wrapping, register A")] +#[test_case(0x3C, register::SingleEightBit::A, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0 }; "increment with half carry, register A")] +// decrement +#[test_case(0x05, register::SingleEightBit::B, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register B")] +#[test_case(0x05, register::SingleEightBit::B, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register B")] +#[test_case(0x05, register::SingleEightBit::B, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register B")] +#[test_case(0x05, register::SingleEightBit::B, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register B")] +#[test_case(0x0D, register::SingleEightBit::C, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register C")] +#[test_case(0x0D, register::SingleEightBit::C, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register C")] +#[test_case(0x0D, register::SingleEightBit::C, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register C")] +#[test_case(0x0D, register::SingleEightBit::C, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register C")] +#[test_case(0x15, register::SingleEightBit::D, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register D")] +#[test_case(0x15, register::SingleEightBit::D, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register D")] +#[test_case(0x15, register::SingleEightBit::D, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register D")] +#[test_case(0x15, register::SingleEightBit::D, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register D")] +#[test_case(0x1D, register::SingleEightBit::E, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register E")] +#[test_case(0x1D, register::SingleEightBit::E, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register E")] +#[test_case(0x1D, register::SingleEightBit::E, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register E")] +#[test_case(0x1D, register::SingleEightBit::E, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register E")] +#[test_case(0x25, register::SingleEightBit::H, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register H")] +#[test_case(0x25, register::SingleEightBit::H, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register H")] +#[test_case(0x25, register::SingleEightBit::H, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register H")] +#[test_case(0x25, register::SingleEightBit::H, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register H")] +#[test_case(0x2D, register::SingleEightBit::L, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register L")] +#[test_case(0x2D, register::SingleEightBit::L, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register L")] +#[test_case(0x2D, register::SingleEightBit::L, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register L")] +#[test_case(0x2D, register::SingleEightBit::L, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register L")] +#[test_case(0x3D, register::SingleEightBit::A, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement, register A")] +#[test_case(0x3D, register::SingleEightBit::A, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping, register A")] +#[test_case(0x3D, register::SingleEightBit::A, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero, register A")] +#[test_case(0x3D, register::SingleEightBit::A, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry, register A")] +fn test_increment_decrement_single_register_flags( opcode: u8, register: register::SingleEightBit, initial_value: u8, @@ -2209,7 +2254,7 @@ fn test_increment_single_register_flags( &mut processor, ( expected_flags.zero, - 0, + expected_flags.subtract, expected_flags.half_carry, // Carry flag should remain unchanged - quick lazy hack to just set this to 1. 0, @@ -2225,16 +2270,18 @@ fn test_increment_single_register_flags( testutil::assert_flags_eq!( processor, (register::Flag::Zero, expected_flags.zero), - (register::Flag::Subtract, 0), + (register::Flag::Subtract, expected_flags.subtract), (register::Flag::HalfCarry, expected_flags.half_carry), // Carry flag should remain unchanged (register::Flag::Carry, 1), ); } -#[test_case(0x05, 0x06; "add one")] -#[test_case(0xFF, 0x00; "add one with wrapping")] -fn test_increment_hl_value(initial_value: u8, expected_value: u8) { +#[test_case(0x34, 0x05, 0x06; "add one")] +#[test_case(0x34, 0xFF, 0x00; "add one with wrapping")] +#[test_case(0x35, 0x05, 0x04; "sub one")] +#[test_case(0x35, 0x000, 0xFF; "sub one with wrapping")] +fn test_increment_decrement_hl_value(opcode: u8, initial_value: u8, expected_value: u8) { let mut processor = Processor::default(); processor .registers @@ -2244,7 +2291,7 @@ fn test_increment_hl_value(initial_value: u8, expected_value: u8) { .set(0xFF23, initial_value) .expect("failed to set memory value"); - let data = [0x34, 0x03]; + let data = [opcode, 0x03]; let (ins, extra_data) = RunnableInstruction::from_data(&data).expect("could not parse instruction"); assert_eq!(extra_data, &[0x03]); @@ -2259,10 +2306,14 @@ fn test_increment_hl_value(initial_value: u8, expected_value: u8) { ); } -#[test_case(0x05, IncrementOperationFlags { zero: 0, half_carry: 0 }; "increment")] -#[test_case(0xFF, IncrementOperationFlags { zero: 1, half_carry: 1 }; "increment with wrapping")] -#[test_case(0x0F, IncrementOperationFlags { zero: 0, half_carry: 1 }; "increment with half carry")] -fn test_increment_hl_flags(initial_value: u8, expected_flags: IncrementOperationFlags) { +#[test_case(0x34, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 0}; "increment")] +#[test_case(0x34, 0xFF, IncrementOperationFlags { zero: 1, half_carry: 1, subtract: 0}; "increment with wrapping")] +#[test_case(0x34, 0x0F, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 0}; "increment with half carry")] +#[test_case(0x35, 0x05, IncrementOperationFlags { zero: 0, half_carry: 0, subtract: 1}; "decrement")] +#[test_case(0x35, 0x01, IncrementOperationFlags { zero: 1, half_carry: 0, subtract: 1}; "decrement to zero")] +#[test_case(0x35, 0x00, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with wrapping")] +#[test_case(0x35, 0x10, IncrementOperationFlags { zero: 0, half_carry: 1, subtract: 1}; "decrement with half carry")] +fn test_increment_decrement_hl_flags(opcode: u8, initial_value: u8, expected_flags: IncrementOperationFlags) { let mut processor = Processor::default(); processor .registers @@ -2277,14 +2328,14 @@ fn test_increment_hl_flags(initial_value: u8, expected_flags: IncrementOperation &mut processor, ( expected_flags.zero, - 0, + expected_flags.subtract, expected_flags.half_carry, // Carry flag should remain unchanged - quick lazy hack to just set this to 1. 0, ), ); - let data = [0x34, 0x03]; + let data = [opcode, 0x03]; let (ins, extra_data) = RunnableInstruction::from_data(&data).expect("could not parse instruction"); assert_eq!(extra_data, &[0x03]); @@ -2293,7 +2344,7 @@ fn test_increment_hl_flags(initial_value: u8, expected_flags: IncrementOperation testutil::assert_flags_eq!( processor, (register::Flag::Zero, expected_flags.zero), - (register::Flag::Subtract, 0), + (register::Flag::Subtract, expected_flags.subtract), (register::Flag::HalfCarry, expected_flags.half_carry), // Carry flag should remain unchanged (register::Flag::Carry, 1), diff --git a/tests/cpu/jsmoo/testdata/disabled/05.json b/tests/cpu/jsmoo/testdata/05.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/05.json rename to tests/cpu/jsmoo/testdata/05.json diff --git a/tests/cpu/jsmoo/testdata/disabled/0d.json b/tests/cpu/jsmoo/testdata/0d.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/0d.json rename to tests/cpu/jsmoo/testdata/0d.json diff --git a/tests/cpu/jsmoo/testdata/disabled/15.json b/tests/cpu/jsmoo/testdata/15.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/15.json rename to tests/cpu/jsmoo/testdata/15.json diff --git a/tests/cpu/jsmoo/testdata/disabled/1d.json b/tests/cpu/jsmoo/testdata/1d.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/1d.json rename to tests/cpu/jsmoo/testdata/1d.json diff --git a/tests/cpu/jsmoo/testdata/disabled/25.json b/tests/cpu/jsmoo/testdata/25.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/25.json rename to tests/cpu/jsmoo/testdata/25.json diff --git a/tests/cpu/jsmoo/testdata/disabled/2d.json b/tests/cpu/jsmoo/testdata/2d.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/2d.json rename to tests/cpu/jsmoo/testdata/2d.json diff --git a/tests/cpu/jsmoo/testdata/disabled/35.json b/tests/cpu/jsmoo/testdata/35.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/35.json rename to tests/cpu/jsmoo/testdata/35.json diff --git a/tests/cpu/jsmoo/testdata/disabled/3d.json b/tests/cpu/jsmoo/testdata/3d.json similarity index 100% rename from tests/cpu/jsmoo/testdata/disabled/3d.json rename to tests/cpu/jsmoo/testdata/3d.json