 Nick Krichevsky
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0c53bd2c6b
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Break up memory parsing module
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2022-04-06 23:06:03 -04:00 |
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Nick Krichevsky
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ad62658980
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Rustdocs
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2022-04-06 22:47:38 -04:00 |
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Nick Krichevsky
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8734a7fc8e
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Make a macro for the transfer module
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2022-04-06 22:43:38 -04:00 |
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Nick Krichevsky
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e5609972c8
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Move instruction parsing into its own module
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2022-04-06 21:01:11 -04:00 |
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Nick Krichevsky
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6d4ffc03ef
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Implement loading to/from A register and fix loading from immediate address
Was pulling from the wrong data in the stream to get the address, and
the test basically was a nop
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2022-04-05 22:13:39 -04:00 |
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Nick Krichevsky
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c491b180fc
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Fix clippy lint
We kinda have to allow this to be this long, lest we ant this method to
devolve into macro hell
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2022-04-05 00:24:25 -04:00 |
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Nick Krichevsky
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28132d60fa
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Add support for loading to A from immediate address
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2022-04-05 00:22:20 -04:00 |
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Nick Krichevsky
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cb535e24c3
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Add loading of addresses in other combined registers than (hl)
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2022-04-05 00:19:19 -04:00 |
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Nick Krichevsky
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e95cd263c5
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Implement load immediate to (hl)
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2022-04-04 23:41:25 -04:00 |
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Nick Krichevsky
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dcaf0588de
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Add load to (hl) instructions
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2022-04-04 23:34:34 -04:00 |
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Nick Krichevsky
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1dc176fd74
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Add load from (hl) instructions
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2022-04-04 23:12:59 -04:00 |
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Nick Krichevsky
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4c6eec264a
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Add basic memory for load instruction backing
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2022-04-04 22:51:56 -04:00 |
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Nick Krichevsky
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af95676b15
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Add parsing of ldr1r2 instructions
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2022-04-04 22:18:15 -04:00 |
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Nick Krichevsky
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92b779d02d
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Add parsing of ldnn instructions
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2022-04-02 11:01:04 -04:00 |
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Nick Krichevsky
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ac6097794d
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Add support for combined registers
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2022-04-01 19:48:13 -04:00 |
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Nick Krichevsky
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607e4ab2df
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Add flag register setting
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2022-04-01 19:21:33 -04:00 |
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Nick Krichevsky
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fc710000a4
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Initial commit. Add registers
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2022-04-01 18:11:09 -04:00 |
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