use ferris_boi::{
    cpu::{instructions::Instruction, Processor},
    register,
};
use test_case::test_case;

#[test_case(0xC0, register::SingleEightBit::B, 0b00000001)]
#[test_case(0xC8, register::SingleEightBit::B, 0b00000010)]
#[test_case(0xD0, register::SingleEightBit::B, 0b00000100)]
#[test_case(0xD8, register::SingleEightBit::B, 0b00001000)]
#[test_case(0xE0, register::SingleEightBit::B, 0b00010000)]
#[test_case(0xE8, register::SingleEightBit::B, 0b00100000)]
#[test_case(0xF0, register::SingleEightBit::B, 0b01000000)]
#[test_case(0xF8, register::SingleEightBit::B, 0b10000000)]
// Register C
#[test_case(0xC1, register::SingleEightBit::C, 0b00000001)]
#[test_case(0xC9, register::SingleEightBit::C, 0b00000010)]
#[test_case(0xD1, register::SingleEightBit::C, 0b00000100)]
#[test_case(0xD9, register::SingleEightBit::C, 0b00001000)]
#[test_case(0xE1, register::SingleEightBit::C, 0b00010000)]
#[test_case(0xE9, register::SingleEightBit::C, 0b00100000)]
#[test_case(0xF1, register::SingleEightBit::C, 0b01000000)]
#[test_case(0xF9, register::SingleEightBit::C, 0b10000000)]
// Register D
#[test_case(0xC2, register::SingleEightBit::D, 0b00000001)]
#[test_case(0xCA, register::SingleEightBit::D, 0b00000010)]
#[test_case(0xD2, register::SingleEightBit::D, 0b00000100)]
#[test_case(0xDA, register::SingleEightBit::D, 0b00001000)]
#[test_case(0xE2, register::SingleEightBit::D, 0b00010000)]
#[test_case(0xEA, register::SingleEightBit::D, 0b00100000)]
#[test_case(0xF2, register::SingleEightBit::D, 0b01000000)]
#[test_case(0xFA, register::SingleEightBit::D, 0b10000000)]
// Register E
#[test_case(0xC3, register::SingleEightBit::E, 0b00000001)]
#[test_case(0xCB, register::SingleEightBit::E, 0b00000010)]
#[test_case(0xD3, register::SingleEightBit::E, 0b00000100)]
#[test_case(0xDB, register::SingleEightBit::E, 0b00001000)]
#[test_case(0xE3, register::SingleEightBit::E, 0b00010000)]
#[test_case(0xEB, register::SingleEightBit::E, 0b00100000)]
#[test_case(0xF3, register::SingleEightBit::E, 0b01000000)]
#[test_case(0xFB, register::SingleEightBit::E, 0b10000000)]
// Register H
#[test_case(0xC4, register::SingleEightBit::H, 0b00000001)]
#[test_case(0xCC, register::SingleEightBit::H, 0b00000010)]
#[test_case(0xD4, register::SingleEightBit::H, 0b00000100)]
#[test_case(0xDC, register::SingleEightBit::H, 0b00001000)]
#[test_case(0xE4, register::SingleEightBit::H, 0b00010000)]
#[test_case(0xEC, register::SingleEightBit::H, 0b00100000)]
#[test_case(0xF4, register::SingleEightBit::H, 0b01000000)]
#[test_case(0xFC, register::SingleEightBit::H, 0b10000000)]
// Register L
#[test_case(0xC5, register::SingleEightBit::L, 0b00000001)]
#[test_case(0xCD, register::SingleEightBit::L, 0b00000010)]
#[test_case(0xD5, register::SingleEightBit::L, 0b00000100)]
#[test_case(0xDD, register::SingleEightBit::L, 0b00001000)]
#[test_case(0xE5, register::SingleEightBit::L, 0b00010000)]
#[test_case(0xED, register::SingleEightBit::L, 0b00100000)]
#[test_case(0xF5, register::SingleEightBit::L, 0b01000000)]
#[test_case(0xFD, register::SingleEightBit::L, 0b10000000)]
// Register A
#[test_case(0xC7, register::SingleEightBit::A, 0b00000001)]
#[test_case(0xCF, register::SingleEightBit::A, 0b00000010)]
#[test_case(0xD7, register::SingleEightBit::A, 0b00000100)]
#[test_case(0xDF, register::SingleEightBit::A, 0b00001000)]
#[test_case(0xE7, register::SingleEightBit::A, 0b00010000)]
#[test_case(0xEF, register::SingleEightBit::A, 0b00100000)]
#[test_case(0xF7, register::SingleEightBit::A, 0b01000000)]
#[test_case(0xFF, register::SingleEightBit::A, 0b10000000)]
fn test_set_register_bit(opcode_variant: u8, register: register::SingleEightBit, expected: u8) {
    let mut processor = Processor::default();

    processor.registers.set_single_8bit_register(register, 0);
    let data = [0xCB, opcode_variant, 0x02];

    let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
    assert_eq!(extra_data, &[0x02]);

    processor.run_instruction(ins);

    assert_eq!(
        expected,
        processor.registers.get_single_8bit_register(register)
    );
}