388 lines
17 KiB
Rust
388 lines
17 KiB
Rust
use ferris_boi::{
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cpu::{instructions::RunnableInstruction, Processor},
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register,
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};
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use test_case::test_case;
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fn set_opposite_of_expected_flags(
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processor: &mut Processor,
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(zero_flag, sub_flag, half_carry_flag, carry_flag): (u8, u8, u8, u8),
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) {
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let invert_flag = |value| {
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if value == 0 {
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1
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} else if value == 1 {
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0
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} else {
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panic!("invalid flag value of {value} ")
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}
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};
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processor
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.registers
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.set_flag_bit(register::Flag::Zero, invert_flag(zero_flag));
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processor
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.registers
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.set_flag_bit(register::Flag::HalfCarry, invert_flag(half_carry_flag));
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, invert_flag(carry_flag));
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processor
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.registers
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.set_flag_bit(register::Flag::Subtract, invert_flag(sub_flag));
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}
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macro_rules! assert_flags_eq {
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($processor: expr, $(($flag: path, $value: expr)),+ $(,)?) => {
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$(
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assert_eq!(
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$value,
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$processor.registers.get_flag_bit($flag),
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"{:?} flag had unexpected value",
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$flag
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);
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)+
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};
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}
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#[test]
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fn test_add_a_to_itself() {
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let mut processor = Processor::default();
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processor.registers.a = 10;
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let data = [0x87, 0x02];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x02]);
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processor.run(&ins);
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assert_eq!(20, processor.registers.a);
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}
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#[test_case(0x80, register::SingleEightBit::B)]
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#[test_case(0x81, register::SingleEightBit::C)]
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#[test_case(0x82, register::SingleEightBit::D)]
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#[test_case(0x83, register::SingleEightBit::E)]
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#[test_case(0x84, register::SingleEightBit::H)]
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#[test_case(0x85, register::SingleEightBit::L)]
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fn test_add_to_a_value(opcode: u8, src: register::SingleEightBit) {
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let mut processor = Processor::default();
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processor.registers.a = 10;
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processor.registers.set_single_8bit_register(src, 20);
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let data = [opcode, 0x02];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x02]);
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processor.run(&ins);
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assert_eq!(30, processor.registers.a);
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}
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#[test_case(0x80, register::SingleEightBit::B, 0x00, 0x00, 1, 0, 0; "zero flag for zero value")]
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#[test_case(0x80, register::SingleEightBit::B, 0x00, 0x01, 0, 0, 0; "no zero flag for non-zero value")]
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#[test_case(0x81, register::SingleEightBit::C, 0x0F, 0x01, 0, 1, 0; "half carry flag")]
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#[test_case(0x81, register::SingleEightBit::C, 0x80, 0x80, 0, 0, 1; "full carry flag")]
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#[test_case(0x81, register::SingleEightBit::C, 0xFF, 0x01, 0, 1, 1; "both full and half carry flag")]
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// 0000 1111
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fn test_add_register_to_a_flags(
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opcode: u8,
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src: register::SingleEightBit,
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a_value: u8,
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src_value: u8,
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zero_flag: u8,
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half_carry_flag: u8,
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carry_flag: u8,
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) {
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let mut processor = Processor::default();
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processor.registers.a = a_value;
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// Set all the register to the opposite we expect to ensure they all get set
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set_opposite_of_expected_flags(&mut processor, (zero_flag, 0, half_carry_flag, carry_flag));
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processor.registers.set_single_8bit_register(src, src_value);
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let data = [opcode, 0x02];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x02]);
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processor.run(&ins);
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, half_carry_flag),
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(register::Flag::Carry, carry_flag),
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);
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}
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#[test]
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fn test_add_hl_addr_to_a_value() {
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let mut processor = Processor::default();
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processor
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.memory
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.set(0xFF00, 0x34)
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.expect("expected to be able to set 0xFF00");
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processor
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.registers
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.set_combined_register(register::Combined::HL, 0xFF00);
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processor.registers.a = 0x12;
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let data = [0x86, 0x02];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x02]);
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processor.run(&ins);
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assert_eq!(0x46, processor.registers.a);
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}
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#[test_case(0x00, 0x00, 1, 0, 0; "zero flag for zero value")]
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#[test_case(0x00, 0x01, 0, 0, 0; "no zero flag for non-zero value")]
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#[test_case(0x0F, 0x01, 0, 1, 0; "half carry flag")]
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#[test_case(0x80, 0x80, 0, 0, 1; "full carry flag")]
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#[test_case(0xFF, 0x01, 0, 1, 1; "both full and half carry flag")]
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fn test_add_hl_addr_to_a_flags(
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a_value: u8,
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hl_addr_value: u8,
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zero_flag: u8,
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half_carry_flag: u8,
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carry_flag: u8,
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) {
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let mut processor = Processor::default();
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processor.registers.a = a_value;
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processor
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.registers
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.set_combined_register(register::Combined::HL, 0xFF00);
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processor
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.memory
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.set(0xFF00, hl_addr_value)
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.expect("expected to set address 0xFF00 but could not");
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// Set all the register to the opposite we expect to ensure they all get set
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set_opposite_of_expected_flags(&mut processor, (zero_flag, 0, half_carry_flag, carry_flag));
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let data = [0x86, 0x01];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x01]);
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processor.run(&ins);
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, half_carry_flag),
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(register::Flag::Carry, carry_flag),
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);
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}
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#[test]
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fn test_add_immediate_to_a_value() {
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let mut processor = Processor::default();
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processor.registers.a = 50;
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let data = [0xC6, 0x13, 0x01];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x01]);
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processor.run(&ins);
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assert_eq!(69, processor.registers.a);
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}
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#[test_case(0x00, 0x00, 1, 0, 0; "zero flag for zero value")]
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#[test_case(0x00, 0x01, 0, 0, 0; "no zero flag for non-zero value")]
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#[test_case(0x0F, 0x01, 0, 1, 0; "half carry flag")]
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#[test_case(0x80, 0x80, 0, 0, 1; "full carry flag")]
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#[test_case(0xFF, 0x01, 0, 1, 1; "both full and half carry flag")]
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fn test_add_immediate_to_a_flags(
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a_value: u8,
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n: u8,
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zero_flag: u8,
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half_carry_flag: u8,
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carry_flag: u8,
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) {
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let mut processor = Processor::default();
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processor.registers.a = a_value;
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// Set all the register to the opposite we expect to ensure they all get set
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set_opposite_of_expected_flags(&mut processor, (zero_flag, 0, half_carry_flag, carry_flag));
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let data = [0xC6, n, 0x01];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x01]);
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processor.run(&ins);
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, half_carry_flag),
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(register::Flag::Carry, carry_flag),
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);
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}
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#[test_case(0x88, 0x12, 0, register::SingleEightBit::B, 0x5, 0x17; "no carry to register b")]
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#[test_case(0x88, 0x12, 1, register::SingleEightBit::B, 0x5, 0x18; "carry to register b")]
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#[test_case(0x89, 0x12, 0, register::SingleEightBit::C, 0x5, 0x17; "no carry to register c")]
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#[test_case(0x89, 0x12, 1, register::SingleEightBit::C, 0x5, 0x18; "carry to register c")]
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#[test_case(0x8A, 0x12, 0, register::SingleEightBit::D, 0x5, 0x17; "no carry to register d")]
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#[test_case(0x8A, 0x12, 1, register::SingleEightBit::D, 0x5, 0x18; "carry to register d")]
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#[test_case(0x8B, 0x12, 0, register::SingleEightBit::E, 0x5, 0x17; "no carry to register e")]
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#[test_case(0x8B, 0x12, 1, register::SingleEightBit::E, 0x5, 0x18; "carry to register e")]
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#[test_case(0x8C, 0x12, 0, register::SingleEightBit::H, 0x5, 0x17; "no carry to register h")]
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#[test_case(0x8C, 0x12, 1, register::SingleEightBit::H, 0x5, 0x18; "carry to register h")]
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#[test_case(0x8D, 0x12, 0, register::SingleEightBit::L, 0x5, 0x17; "no carry to register l")]
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#[test_case(0x8D, 0x12, 1, register::SingleEightBit::L, 0x5, 0x18; "carry to register l")]
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fn test_add_with_carry_to_a_value(
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opcode: u8,
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initial_value: u8,
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carry_bit: u8,
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operand_register: register::SingleEightBit,
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operand: u8,
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expected_value: u8,
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) {
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let mut processor = Processor::default();
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processor.registers.a = initial_value;
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processor
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.registers
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.set_single_8bit_register(operand_register, operand);
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, carry_bit);
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let data = [opcode, 0x01];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x01]);
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processor.run(&ins);
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assert_eq!(expected_value, processor.registers.a);
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}
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// these parameters are like impossible to read but I can't think of a nicer way to do this right now
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// B register
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#[test_case(0x88, 0x12, 0, register::SingleEightBit::B, 0x5, 0, 0, 0; "no carry bit set, results in no flags, register b")]
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#[test_case(0x88, 0x12, 1, register::SingleEightBit::B, 0x5, 0, 0, 0; "carry bit set, results in no flags, register b")]
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#[test_case(0x88, 0x00, 0, register::SingleEightBit::B, 0x0, 1, 0, 0; "no carry bit set, zero operands result in zero flag set, register b")]
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#[test_case(0x88, 0x00, 1, register::SingleEightBit::B, 0x0, 0, 0, 0; "carry bit set, zero operands result in no zero flag set, register b")]
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#[test_case(0x88, 0x0F, 0, register::SingleEightBit::B, 0x1, 0, 1, 0; "no carry bit, half carry, register b")]
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#[test_case(0x88, 0x0F, 1, register::SingleEightBit::B, 0x1, 0, 1, 0; "carry bit, half carry, register b")]
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#[test_case(0x88, 0x0F, 0, register::SingleEightBit::B, 0x0F, 0, 1, 0; "no carry bit, full carry, register b")]
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#[test_case(0x88, 0x0F, 1, register::SingleEightBit::B, 0x0F, 0, 1, 0; "carry bit, full carry, register b")]
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#[test_case(0x88, 0xFF, 1, register::SingleEightBit::B, 0xFF, 0, 1, 1; "carry bit, both carries, register b")]
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// C register
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#[test_case(0x89, 0x12, 0, register::SingleEightBit::C, 0x5, 0, 0, 0; "no carry bit set, results in no flags, register c")]
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#[test_case(0x89, 0x12, 1, register::SingleEightBit::C, 0x5, 0, 0, 0; "carry bit set, results in no flags, register c")]
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#[test_case(0x89, 0x00, 0, register::SingleEightBit::C, 0x0, 1, 0, 0; "no carry bit set, zero operands result in zero flag set, register c")]
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#[test_case(0x89, 0x00, 1, register::SingleEightBit::C, 0x0, 0, 0, 0; "carry bit set, zero operands result in no zero flag set, register c")]
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#[test_case(0x89, 0x0F, 0, register::SingleEightBit::C, 0x1, 0, 1, 0; "no carry bit, half carry, register c")]
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#[test_case(0x89, 0x0F, 1, register::SingleEightBit::C, 0x1, 0, 1, 0; "carry bit, half carry, register c")]
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#[test_case(0x89, 0x0F, 0, register::SingleEightBit::C, 0x0F, 0, 1, 0; "no carry bit, full carry, register c")]
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#[test_case(0x89, 0x0F, 1, register::SingleEightBit::C, 0x0F, 0, 1, 0; "carry bit, full carry, register c")]
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#[test_case(0x89, 0xFF, 1, register::SingleEightBit::C, 0xFF, 0, 1, 1; "carry bit, both carries, register c")]
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// D register
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#[test_case(0x8A, 0x12, 0, register::SingleEightBit::D, 0x5, 0, 0, 0; "no carry bit set, results in no flags, register d")]
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#[test_case(0x8A, 0x12, 1, register::SingleEightBit::D, 0x5, 0, 0, 0; "carry bit set, results in no flags, register d")]
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#[test_case(0x8A, 0x00, 0, register::SingleEightBit::D, 0x0, 1, 0, 0; "no carry bit set, zero operands result in zero flag set, register d")]
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#[test_case(0x8A, 0x00, 1, register::SingleEightBit::D, 0x0, 0, 0, 0; "carry bit set, zero operands result in no zero flag set, register d")]
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#[test_case(0x8A, 0x0F, 0, register::SingleEightBit::D, 0x1, 0, 1, 0; "no carry bit, half carry, register d")]
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#[test_case(0x8A, 0x0F, 1, register::SingleEightBit::D, 0x1, 0, 1, 0; "carry bit, half carry, register d")]
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#[test_case(0x8A, 0x0F, 0, register::SingleEightBit::D, 0x0F, 0, 1, 0; "no carry bit, full carry, register d")]
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#[test_case(0x8A, 0x0F, 1, register::SingleEightBit::D, 0x0F, 0, 1, 0; "carry bit, full carry, register d")]
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#[test_case(0x8A, 0xFF, 1, register::SingleEightBit::D, 0xFF, 0, 1, 1; "carry bit, both carries, register d")]
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// E register
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#[test_case(0x8B, 0x12, 0, register::SingleEightBit::E, 0x5, 0, 0, 0; "no carry bit set, results in no flags, register e")]
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#[test_case(0x8B, 0x12, 1, register::SingleEightBit::E, 0x5, 0, 0, 0; "carry bit set, results in no flags, register e")]
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#[test_case(0x8B, 0x00, 0, register::SingleEightBit::E, 0x0, 1, 0, 0; "no carry bit set, zero operands result in zero flag set, register e")]
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#[test_case(0x8B, 0x00, 1, register::SingleEightBit::E, 0x0, 0, 0, 0; "carry bit set, zero operands result in no zero flag set, register e")]
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#[test_case(0x8B, 0x0F, 0, register::SingleEightBit::E, 0x1, 0, 1, 0; "no carry bit, half carry, register e")]
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#[test_case(0x8B, 0x0F, 1, register::SingleEightBit::E, 0x1, 0, 1, 0; "carry bit, half carry, register e")]
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#[test_case(0x8B, 0x0F, 0, register::SingleEightBit::E, 0x0F, 0, 1, 0; "no carry bit, full carry, register e")]
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#[test_case(0x8B, 0x0F, 1, register::SingleEightBit::E, 0x0F, 0, 1, 0; "carry bit, full carry, register e")]
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#[test_case(0x8B, 0xFF, 1, register::SingleEightBit::E, 0xFF, 0, 1, 1; "carry bit, both carries, register e")]
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// H register
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#[test_case(0x8C, 0x12, 0, register::SingleEightBit::H, 0x5, 0, 0, 0; "no carry bit set, results in no flags, register h")]
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#[test_case(0x8C, 0x12, 1, register::SingleEightBit::H, 0x5, 0, 0, 0; "carry bit set, results in no flags, register h")]
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#[test_case(0x8C, 0x00, 0, register::SingleEightBit::H, 0x0, 1, 0, 0; "no carry bit set, zero operands result in zero flag set, register h")]
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#[test_case(0x8C, 0x00, 1, register::SingleEightBit::H, 0x0, 0, 0, 0; "carry bit set, zero operands result in no zero flag set, register h")]
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#[test_case(0x8C, 0x0F, 0, register::SingleEightBit::H, 0x1, 0, 1, 0; "no carry bit, half carry, register h")]
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#[test_case(0x8C, 0x0F, 1, register::SingleEightBit::H, 0x1, 0, 1, 0; "carry bit, half carry, register h")]
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#[test_case(0x8C, 0x0F, 0, register::SingleEightBit::H, 0x0F, 0, 1, 0; "no carry bit, full carry, register h")]
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#[test_case(0x8C, 0x0F, 1, register::SingleEightBit::H, 0x0F, 0, 1, 0; "carry bit, full carry, register h")]
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#[test_case(0x8C, 0xFF, 1, register::SingleEightBit::H, 0xFF, 0, 1, 1; "carry bit, both carries, register h")]
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// L register
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#[test_case(0x8D, 0x12, 0, register::SingleEightBit::L, 0x5, 0, 0, 0; "no carry bit set, results in no flags, register l")]
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#[test_case(0x8D, 0x12, 1, register::SingleEightBit::L, 0x5, 0, 0, 0; "carry bit set, results in no flags, register l")]
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#[test_case(0x8D, 0x00, 0, register::SingleEightBit::L, 0x0, 1, 0, 0; "no carry bit set, zero operands result in zero flag set, register l")]
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#[test_case(0x8D, 0x00, 1, register::SingleEightBit::L, 0x0, 0, 0, 0; "carry bit set, zero operands result in no zero flag set, register l")]
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#[test_case(0x8D, 0x0F, 0, register::SingleEightBit::L, 0x1, 0, 1, 0; "no carry bit, half carry, register l")]
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#[test_case(0x8D, 0x0F, 1, register::SingleEightBit::L, 0x1, 0, 1, 0; "carry bit, half carry, register l")]
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#[test_case(0x8D, 0x0F, 0, register::SingleEightBit::L, 0x0F, 0, 1, 0; "no carry bit, full carry, register l")]
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#[test_case(0x8D, 0x0F, 1, register::SingleEightBit::L, 0x0F, 0, 1, 0; "carry bit, full carry, register l")]
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#[test_case(0x8D, 0xFF, 1, register::SingleEightBit::L, 0xFF, 0, 1, 1; "carry bit, both carries, register l")]
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fn test_add_with_carry_to_a_flags(
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opcode: u8,
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initial_value: u8,
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carry_bit: u8,
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operand_register: register::SingleEightBit,
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operand: u8,
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expected_zero_flag: u8,
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expected_half_carry_flag: u8,
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expected_carry_flag: u8,
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) {
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let mut processor = Processor::default();
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processor.registers.a = initial_value;
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processor
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.registers
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.set_single_8bit_register(operand_register, operand);
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// Set all the register to the opposite we expect to ensure they all get set
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set_opposite_of_expected_flags(
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&mut processor,
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(
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expected_zero_flag,
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0,
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expected_half_carry_flag,
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expected_carry_flag,
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),
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);
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// ...except for the carry bit, which we must set for the test
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, carry_bit);
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let data = [opcode, 0x01];
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let (ins, extra_data) =
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RunnableInstruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x01]);
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processor.run(&ins);
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|
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, expected_zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, expected_half_carry_flag),
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(register::Flag::Carry, expected_carry_flag),
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|
);
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}
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