329 lines
13 KiB
Rust
329 lines
13 KiB
Rust
use ferris_boi::{
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cpu::{instructions::Instruction, Processor},
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register,
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};
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use test_case::test_case;
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// lol going from a register to itself is kind of a weird thing to test
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#[test_case(0x7F, register::SingleEightBit::A, register::SingleEightBit::A)]
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#[test_case(0x78, register::SingleEightBit::A, register::SingleEightBit::B)]
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#[test_case(0x79, register::SingleEightBit::A, register::SingleEightBit::C)]
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#[test_case(0x7A, register::SingleEightBit::A, register::SingleEightBit::D)]
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#[test_case(0x7B, register::SingleEightBit::A, register::SingleEightBit::E)]
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#[test_case(0x7C, register::SingleEightBit::A, register::SingleEightBit::H)]
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#[test_case(0x7D, register::SingleEightBit::A, register::SingleEightBit::L)]
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#[test_case(0x40, register::SingleEightBit::B, register::SingleEightBit::B)]
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#[test_case(0x41, register::SingleEightBit::B, register::SingleEightBit::C)]
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#[test_case(0x42, register::SingleEightBit::B, register::SingleEightBit::D)]
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#[test_case(0x43, register::SingleEightBit::B, register::SingleEightBit::E)]
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#[test_case(0x44, register::SingleEightBit::B, register::SingleEightBit::H)]
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#[test_case(0x45, register::SingleEightBit::B, register::SingleEightBit::L)]
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#[test_case(0x48, register::SingleEightBit::C, register::SingleEightBit::B)]
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#[test_case(0x49, register::SingleEightBit::C, register::SingleEightBit::C)]
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#[test_case(0x4A, register::SingleEightBit::C, register::SingleEightBit::D)]
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#[test_case(0x4B, register::SingleEightBit::C, register::SingleEightBit::E)]
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#[test_case(0x4C, register::SingleEightBit::C, register::SingleEightBit::H)]
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#[test_case(0x4D, register::SingleEightBit::C, register::SingleEightBit::L)]
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#[test_case(0x50, register::SingleEightBit::D, register::SingleEightBit::B)]
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#[test_case(0x51, register::SingleEightBit::D, register::SingleEightBit::C)]
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#[test_case(0x52, register::SingleEightBit::D, register::SingleEightBit::D)]
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#[test_case(0x53, register::SingleEightBit::D, register::SingleEightBit::E)]
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#[test_case(0x54, register::SingleEightBit::D, register::SingleEightBit::H)]
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#[test_case(0x55, register::SingleEightBit::D, register::SingleEightBit::L)]
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#[test_case(0x58, register::SingleEightBit::E, register::SingleEightBit::B)]
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#[test_case(0x59, register::SingleEightBit::E, register::SingleEightBit::C)]
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#[test_case(0x5A, register::SingleEightBit::E, register::SingleEightBit::D)]
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#[test_case(0x5B, register::SingleEightBit::E, register::SingleEightBit::E)]
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#[test_case(0x5C, register::SingleEightBit::E, register::SingleEightBit::H)]
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#[test_case(0x5D, register::SingleEightBit::E, register::SingleEightBit::L)]
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#[test_case(0x60, register::SingleEightBit::H, register::SingleEightBit::B)]
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#[test_case(0x61, register::SingleEightBit::H, register::SingleEightBit::C)]
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#[test_case(0x62, register::SingleEightBit::H, register::SingleEightBit::D)]
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#[test_case(0x63, register::SingleEightBit::H, register::SingleEightBit::E)]
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#[test_case(0x64, register::SingleEightBit::H, register::SingleEightBit::H)]
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#[test_case(0x65, register::SingleEightBit::H, register::SingleEightBit::L)]
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#[test_case(0x68, register::SingleEightBit::L, register::SingleEightBit::B)]
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#[test_case(0x69, register::SingleEightBit::L, register::SingleEightBit::C)]
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#[test_case(0x6A, register::SingleEightBit::L, register::SingleEightBit::D)]
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#[test_case(0x6B, register::SingleEightBit::L, register::SingleEightBit::E)]
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#[test_case(0x6C, register::SingleEightBit::L, register::SingleEightBit::H)]
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#[test_case(0x6D, register::SingleEightBit::L, register::SingleEightBit::L)]
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#[test_case(0x47, register::SingleEightBit::B, register::SingleEightBit::A)]
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#[test_case(0x4F, register::SingleEightBit::C, register::SingleEightBit::A)]
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#[test_case(0x57, register::SingleEightBit::D, register::SingleEightBit::A)]
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#[test_case(0x5F, register::SingleEightBit::E, register::SingleEightBit::A)]
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#[test_case(0x67, register::SingleEightBit::H, register::SingleEightBit::A)]
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#[test_case(0x6F, register::SingleEightBit::L, register::SingleEightBit::A)]
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fn test_load_register(
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load_opcode: u8,
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dst_register: register::SingleEightBit,
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src_register: register::SingleEightBit,
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) {
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let mut processor = Processor::default();
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processor
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.registers
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.set_single_8bit_register(src_register, 0x45);
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let data = [load_opcode, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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// assert our extra data after the instruction is returned
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(
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0x45,
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processor.registers.get_single_8bit_register(dst_register)
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);
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}
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#[test_case(0x3E, register::SingleEightBit::A)]
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#[test_case(0x06, register::SingleEightBit::B)]
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#[test_case(0x0E, register::SingleEightBit::C)]
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#[test_case(0x16, register::SingleEightBit::D)]
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#[test_case(0x1E, register::SingleEightBit::E)]
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#[test_case(0x26, register::SingleEightBit::H)]
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#[test_case(0x2E, register::SingleEightBit::L)]
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fn test_load_immediate(load_opcode: u8, expected_register: register::SingleEightBit) {
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let mut processor = Processor::default();
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let data = [load_opcode, 0x23, 0x00, 0x01];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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// assert our extra data after the instruction is returned
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// this data is just garbage; no idea if it's a valid instruction
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assert_eq!(extra_data, &[0x00, 0x01]);
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processor.run_instruction(ins);
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assert_eq!(
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0x23,
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processor
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.registers
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.get_single_8bit_register(expected_register)
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);
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}
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#[test_case(0x7E, register::Combined::HL, register::SingleEightBit::A)]
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#[test_case(0x46, register::Combined::HL, register::SingleEightBit::B)]
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#[test_case(0x4E, register::Combined::HL, register::SingleEightBit::C)]
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#[test_case(0x56, register::Combined::HL, register::SingleEightBit::D)]
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#[test_case(0x5E, register::Combined::HL, register::SingleEightBit::E)]
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#[test_case(0x66, register::Combined::HL, register::SingleEightBit::H)]
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#[test_case(0x6E, register::Combined::HL, register::SingleEightBit::L)]
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#[test_case(0x0A, register::Combined::BC, register::SingleEightBit::A)]
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#[test_case(0x1A, register::Combined::DE, register::SingleEightBit::A)]
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fn test_load_from_memory(
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opcode: u8,
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expected_deref_register: register::Combined,
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expected_register: register::SingleEightBit,
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) {
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let mut processor = Processor::default();
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let set_val = processor.memory.set(0xCCDD, 105);
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assert_eq!(105, set_val.unwrap());
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processor
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.registers
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.set_combined_register(expected_deref_register, 0xCCDD);
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let data = [opcode, 0x10, 0x20];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse isntruction");
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assert_eq!(extra_data, &[0x10, 0x20]);
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processor.run_instruction(ins);
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assert_eq!(
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105,
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processor
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.registers
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.get_single_8bit_register(expected_register)
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);
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}
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#[test_case(0x70, register::Combined::HL, register::SingleEightBit::B)]
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#[test_case(0x71, register::Combined::HL, register::SingleEightBit::C)]
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#[test_case(0x72, register::Combined::HL, register::SingleEightBit::D)]
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#[test_case(0x73, register::Combined::HL, register::SingleEightBit::E)]
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#[test_case(0x74, register::Combined::HL, register::SingleEightBit::H)]
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#[test_case(0x75, register::Combined::HL, register::SingleEightBit::L)]
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#[test_case(0x02, register::Combined::BC, register::SingleEightBit::A)]
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#[test_case(0x12, register::Combined::DE, register::SingleEightBit::A)]
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#[test_case(0x77, register::Combined::HL, register::SingleEightBit::A)]
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fn test_load_to_memory(
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opcode: u8,
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expected_deref_register: register::Combined,
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expected_register: register::SingleEightBit,
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) {
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let mut processor = Processor::default();
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// This test does a bit of a sneaky - because we want to use CC as the high/low addresses
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// in the H/L variants of these tests, but we also want to use it store addreses, we must
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// be careful that the stored immediate value is also part of the address in these cases.
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processor
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.registers
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.set_single_8bit_register(expected_register, 0xCC);
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processor
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.registers
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.set_combined_register(expected_deref_register, 0xCCCC);
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let data = [opcode, 0x10, 0x20];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x10, 0x20]);
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processor.run_instruction(ins);
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assert_eq!(0xCC, processor.memory.get(0xCCCC).unwrap());
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}
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#[test]
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fn test_load_immediate_to_memory() {
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let mut processor = Processor::default();
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processor
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.registers
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.set_combined_register(register::Combined::HL, 0xCCDE);
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let data = [0x36, 0x1D, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(0x1D, processor.memory.get(0xCCDE).unwrap());
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}
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#[test]
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fn test_load_from_immediate_address() {
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let mut processor = Processor::default();
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processor
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.memory
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.set(0xCCDE, 105)
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.expect("failed to set memory value");
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let data = [0xFA, 0xDE, 0xCC, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(105, processor.registers.a);
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}
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#[test]
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fn test_load_to_immadiate_address() {
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let mut processor = Processor::default();
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processor.registers.a = 105;
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let data = [0xEA, 0xDE, 0xCC, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(105, processor.memory.get(0xCCDE).unwrap());
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}
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#[test]
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fn test_load_from_io_register_zone() {
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let mut processor = Processor::default();
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processor
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.memory
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.set(0xFF64, 10)
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.expect("could not set memory value");
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processor.registers.c = 0x64;
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let data = [0xF2, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(10, processor.registers.a);
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}
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#[test]
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fn test_load_to_io_register_zone() {
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let mut processor = Processor::default();
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processor.registers.c = 0x64;
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processor.registers.a = 10;
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let data = [0xE2, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(10, processor.memory.get(0xFF64).unwrap());
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}
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#[test_case(0x3A, 0x64, 0x63)]
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#[test_case(0x2A, 0x64, 0x65)]
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fn test_load_from_register_address_then_do_arithmetic(
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opcode: u8,
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hl_value_before: u16,
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hl_value_after: u16,
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) {
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let mut processor = Processor::default();
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processor
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.registers
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.set_combined_register(register::Combined::HL, hl_value_before);
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processor
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.memory
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.set(hl_value_before.into(), 10)
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.expect("failed to set memory value");
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let data = [opcode, 0x00];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x00]);
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processor.run_instruction(ins);
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assert_eq!(10, processor.registers.a);
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assert_eq!(
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hl_value_after,
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processor
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.registers
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.get_combined_register(register::Combined::HL)
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);
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}
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#[test]
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fn test_load_to_io_register_zone_by_immediate() {
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let mut processor = Processor::default();
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processor.registers.a = 0xAF;
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let data = [0xE0, 0x05, 0x06];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x06]);
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processor.run_instruction(ins);
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assert_eq!(0xAF, processor.memory.get(0xFF05).unwrap());
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}
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#[test]
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fn test_load_from_io_register_zone_by_immediate() {
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let mut processor = Processor::default();
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processor
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.memory
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.set(0xFF05, 0xAF)
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.expect("failed to set memory value");
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let data = [0xF0, 0x05, 0x06];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x06]);
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processor.run_instruction(ins);
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assert_eq!(0xAF, processor.registers.a);
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}
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#[test]
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fn test_load_from_bottom_of_so_to_immediate_address() {
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let mut processor = Processor::default();
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processor.registers.stack_pointer = 0xABCD;
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let data = [0x08, 0xAA, 0xFF, 0x06];
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let (ins, extra_data) = Instruction::from_data(&data).expect("could not parse instruction");
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assert_eq!(extra_data, &[0x06]);
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processor.run_instruction(ins);
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let bottom_stored_value = processor.memory.get_from(0xFFAA).unwrap().get();
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let top_stored_value = processor.memory.get_from(0xFFAB).unwrap().get();
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assert_eq!(0xCD, bottom_stored_value);
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assert_eq!(0xAB, top_stored_value);
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}
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