Assert number of cycles taken per instruction in jsmoo tests, correct incorrect cycle counts

old-bit-manip
Nick Krichevsky 2023-11-18 21:12:42 -05:00
parent 8293244d6c
commit 3a91f76f1e
5 changed files with 10 additions and 6 deletions

View File

@ -14,7 +14,7 @@ mod run;
pub struct Processor {
pub registers: Registers,
pub memory: Memory,
num_cycles: u64,
pub num_cycles: u128,
}
impl Processor {
@ -48,7 +48,7 @@ impl Processor {
panic!("Fatal CPU error occured: {err}")
}
self.num_cycles += u64::from(instruction.cycles);
self.num_cycles += u128::from(instruction.cycles);
}
fn load_from_register_to_register_address(

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@ -53,7 +53,7 @@ fn build_add_hl_to_register_data(operand_register: SixteenBit) -> ParseOutput {
instruction: Instruction::SixteenBitArithmetic(
SixteenBitArithmeticInstruction::AddRegisterToHL { operand_register },
),
cycles: 2,
cycles: 8,
},
1,
)
@ -65,7 +65,7 @@ fn build_inc_register_data(operand_register: SixteenBit) -> ParseOutput {
instruction: Instruction::SixteenBitArithmetic(
SixteenBitArithmeticInstruction::IncrementRegister { operand_register },
),
cycles: 2,
cycles: 8,
},
1,
)
@ -77,7 +77,7 @@ fn build_dec_register_data(operand_register: SixteenBit) -> ParseOutput {
instruction: Instruction::SixteenBitArithmetic(
SixteenBitArithmeticInstruction::DecrementRegister { operand_register },
),
cycles: 2,
cycles: 8,
},
1,
)

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@ -33,7 +33,7 @@ fn make_load_between_register_data(
instruction: Instruction::SixteenBitLoad(
SixteenBitLoadInstruction::LoadBetweenRegisters { dst, src },
),
cycles: 4,
cycles: 8,
},
1,
)

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@ -25,4 +25,5 @@ struct TestCase {
name: String,
initial: TestState,
r#final: TestState,
cycles: Vec<serde_json::Value>
}

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@ -90,5 +90,8 @@ fn test_jsmoo_test(filename: &str) {
assert_eq!(stored_val, value);
}
let num_cycles_expected = test_case.cycles.len() * 4;
assert_eq!(u128::try_from(num_cycles_expected).unwrap(), processor.num_cycles);
}
}