Reduce repetition in flags tests
parent
f0c0e818c9
commit
70db1fe62a
175
src/cpu.rs
175
src/cpu.rs
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@ -121,6 +121,50 @@ mod tests {
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use super::*;
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use test_case::test_case;
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fn set_opposite_of_expected_flags(
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processor: &mut Processor,
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(zero_flag, sub_flag, half_carry_flag, carry_flag): (u8, u8, u8, u8),
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) {
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let invert_flag = |value| {
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if value == 0 {
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1
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} else if value == 1 {
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0
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} else {
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panic!("invalid flag value of {value} ")
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}
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};
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processor
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.registers
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.set_flag_bit(register::Flag::Zero, invert_flag(zero_flag));
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processor
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.registers
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.set_flag_bit(register::Flag::HalfCarry, invert_flag(half_carry_flag));
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, invert_flag(carry_flag));
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processor
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.registers
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.set_flag_bit(register::Flag::Subtract, invert_flag(sub_flag));
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}
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macro_rules! assert_flags_eq {
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($processor: expr, $(($flag: path, $value: expr)),+ $(,)?) => {
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$(
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assert_eq!(
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$value,
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$processor.registers.get_flag_bit($flag),
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"{:?} flag had unexpected value",
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$flag
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);
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)+
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};
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}
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#[test_case(0x3E, register::SingleEightBit::A)]
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#[test_case(0x06, register::SingleEightBit::B)]
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#[test_case(0x0E, register::SingleEightBit::C)]
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@ -661,8 +705,6 @@ mod tests {
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assert_eq!(20, processor.registers.a);
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}
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// TODO: These add tests are almost entirely copy paste - we should find some way to break them up
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#[test_case(0x80, register::SingleEightBit::B)]
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#[test_case(0x81, register::SingleEightBit::C)]
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#[test_case(0x82, register::SingleEightBit::D)]
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@ -703,20 +745,7 @@ mod tests {
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processor.registers.a = a_value;
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// Set all the register to the opposite we expect to ensure they all get set
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processor
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.registers
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.set_flag_bit(register::Flag::Zero, if zero_flag == 1 { 0 } else { 1 });
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processor.registers.set_flag_bit(
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register::Flag::HalfCarry,
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if half_carry_flag == 1 { 0 } else { 1 },
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);
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, if carry_flag == 1 { 0 } else { 1 });
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processor
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.registers
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.set_flag_bit(register::Flag::Subtract, 1);
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set_opposite_of_expected_flags(&mut processor, (zero_flag, 0, half_carry_flag, carry_flag));
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processor.registers.set_single_8bit_register(src, src_value);
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let data = [opcode, 0x02];
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@ -727,28 +756,12 @@ mod tests {
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processor.run(&ins);
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assert_eq!(
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zero_flag,
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processor.registers.get_flag_bit(register::Flag::Zero),
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"zero flag did not match",
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);
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assert_eq!(
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0,
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processor.registers.get_flag_bit(register::Flag::Subtract),
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"sub flag did not match",
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);
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assert_eq!(
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half_carry_flag,
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processor.registers.get_flag_bit(register::Flag::HalfCarry),
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"half carry flag did not match"
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);
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assert_eq!(
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carry_flag,
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processor.registers.get_flag_bit(register::Flag::Carry),
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"carry flag did not match"
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, half_carry_flag),
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(register::Flag::Carry, carry_flag),
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);
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}
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@ -801,20 +814,7 @@ mod tests {
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.expect("expected to set address 0xFF00 but could not");
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// Set all the register to the opposite we expect to ensure they all get set
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processor
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.registers
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.set_flag_bit(register::Flag::Zero, if zero_flag == 1 { 0 } else { 1 });
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processor.registers.set_flag_bit(
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register::Flag::HalfCarry,
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if half_carry_flag == 1 { 0 } else { 1 },
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);
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, if carry_flag == 1 { 0 } else { 1 });
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processor
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.registers
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.set_flag_bit(register::Flag::Subtract, 1);
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set_opposite_of_expected_flags(&mut processor, (zero_flag, 0, half_carry_flag, carry_flag));
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let data = [0x86, 0x01];
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let (ins, extra_data) =
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@ -823,28 +823,12 @@ mod tests {
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processor.run(&ins);
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assert_eq!(
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zero_flag,
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processor.registers.get_flag_bit(register::Flag::Zero),
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"zero flag did not match",
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);
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assert_eq!(
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0,
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processor.registers.get_flag_bit(register::Flag::Subtract),
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"sub flag did not match",
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);
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assert_eq!(
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half_carry_flag,
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processor.registers.get_flag_bit(register::Flag::HalfCarry),
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"half carry flag did not match"
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);
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assert_eq!(
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carry_flag,
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processor.registers.get_flag_bit(register::Flag::Carry),
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"carry flag did not match"
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, half_carry_flag),
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(register::Flag::Carry, carry_flag),
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);
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}
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@ -879,20 +863,7 @@ mod tests {
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processor.registers.a = a_value;
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// Set all the register to the opposite we expect to ensure they all get set
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processor
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.registers
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.set_flag_bit(register::Flag::Zero, if zero_flag == 1 { 0 } else { 1 });
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processor.registers.set_flag_bit(
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register::Flag::HalfCarry,
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if half_carry_flag == 1 { 0 } else { 1 },
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);
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, if carry_flag == 1 { 0 } else { 1 });
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processor
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.registers
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.set_flag_bit(register::Flag::Subtract, 1);
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set_opposite_of_expected_flags(&mut processor, (zero_flag, 0, half_carry_flag, carry_flag));
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let data = [0xC6, n, 0x01];
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let (ins, extra_data) =
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@ -901,28 +872,12 @@ mod tests {
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processor.run(&ins);
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assert_eq!(
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zero_flag,
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processor.registers.get_flag_bit(register::Flag::Zero),
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"zero flag did not match",
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);
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assert_eq!(
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0,
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processor.registers.get_flag_bit(register::Flag::Subtract),
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"sub flag did not match",
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);
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assert_eq!(
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half_carry_flag,
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processor.registers.get_flag_bit(register::Flag::HalfCarry),
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"half carry flag did not match"
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);
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assert_eq!(
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carry_flag,
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processor.registers.get_flag_bit(register::Flag::Carry),
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"carry flag did not match"
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assert_flags_eq!(
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processor,
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(register::Flag::Zero, zero_flag),
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(register::Flag::Subtract, 0),
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(register::Flag::HalfCarry, half_carry_flag),
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(register::Flag::Carry, carry_flag),
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);
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}
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}
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