parent
70db1fe62a
commit
16c275282e
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@ -21,7 +21,7 @@ impl Processor {
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fn run(&mut self, instruction: &RunnableInstruction) {
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let run_res = run::run_instruction(self, &instruction.instruction);
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if let Err(err) = run_res {
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panic!("Fatal CPU error occured: {}", err)
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panic!("Fatal CPU error occured: {err}")
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}
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self.num_cycles += u64::from(instruction.cycles);
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@ -55,5 +55,5 @@ pub fn next_instruction(data: &[u8]) -> ParseResult {
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}
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fn get_opcode_from_data(data: &[u8]) -> Result<u8, Error> {
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data.get(0).copied().ok_or(Error::NoData)
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data.first().copied().ok_or(Error::NoData)
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}
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@ -84,21 +84,18 @@ fn set_addition_flags(processor: &mut Processor, total: u8, half_carry: bool, ca
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processor.registers.set_flag_bit(
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register::Flag::Zero,
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// carry must be false, as if it's true, the value is indeed > 0
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if total == 0 && !carry { 1 } else { 0 },
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(total == 0 && !carry).into(),
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);
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let half_carry_bit = if half_carry { 1 } else { 0 };
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processor
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.registers
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.set_flag_bit(register::Flag::Subtract, 0);
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processor
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.registers
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.set_flag_bit(register::Flag::HalfCarry, half_carry_bit);
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.set_flag_bit(register::Flag::HalfCarry, half_carry.into());
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let full_carry_bit = if carry { 1 } else { 0 };
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, full_carry_bit);
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.set_flag_bit(register::Flag::Carry, carry.into());
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}
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@ -33,14 +33,12 @@ impl InstructionRunner<SixteenBitLoadInstruction> for SixteenBitLoadRunner {
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let (new_sp, half_carry, carry) = current_sp.add_with_carry(offset);
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let half_carry_bit = if half_carry { 1 } else { 0 };
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let carry_bit = if carry { 1 } else { 0 };
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processor
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.registers
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.set_flag_bit(register::Flag::Carry, carry_bit);
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.set_flag_bit(register::Flag::Carry, carry.into());
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processor
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.registers
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.set_flag_bit(register::Flag::HalfCarry, half_carry_bit);
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.set_flag_bit(register::Flag::HalfCarry, half_carry.into());
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// Manual says we reset these here.
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processor
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