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Fix some clippy lints 

Back on the horse...
jsmoo
Nick Krichevsky 2023-04-15 15:06:00 -04:00
parent 70db1fe62a
commit 16c275282e
4 changed files with 7 additions and 12 deletions
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2
src/cpu.rs
View File

@ -21,7 +21,7 @@ impl Processor {
fn run(&mut self, instruction: &RunnableInstruction) { fn run(&mut self, instruction: &RunnableInstruction) {
let run_res = run::run_instruction(self, &instruction.instruction); let run_res = run::run_instruction(self, &instruction.instruction);
if let Err(err) = run_res { if let Err(err) = run_res {
panic!("Fatal CPU error occured: {}", err) panic!("Fatal CPU error occured: {err}")
} }
self.num_cycles += u64::from(instruction.cycles); self.num_cycles += u64::from(instruction.cycles);

2
src/cpu/parse.rs
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@ -55,5 +55,5 @@ pub fn next_instruction(data: &[u8]) -> ParseResult {
} }
fn get_opcode_from_data(data: &[u8]) -> Result<u8, Error> { fn get_opcode_from_data(data: &[u8]) -> Result<u8, Error> {
data.get(0).copied().ok_or(Error::NoData) data.first().copied().ok_or(Error::NoData)
} }

9
src/cpu/run/arith8.rs
View File

@ -84,21 +84,18 @@ fn set_addition_flags(processor: &mut Processor, total: u8, half_carry: bool, ca
processor.registers.set_flag_bit( processor.registers.set_flag_bit(
register::Flag::Zero, register::Flag::Zero,
// carry must be false, as if it's true, the value is indeed > 0 // carry must be false, as if it's true, the value is indeed > 0
if total == 0 && !carry { 1 } else { 0 }, (total == 0 && !carry).into(),
); );
let half_carry_bit = if half_carry { 1 } else { 0 };
processor processor
.registers .registers
.set_flag_bit(register::Flag::Subtract, 0); .set_flag_bit(register::Flag::Subtract, 0);
processor processor
.registers .registers
.set_flag_bit(register::Flag::HalfCarry, half_carry_bit); .set_flag_bit(register::Flag::HalfCarry, half_carry.into());
let full_carry_bit = if carry { 1 } else { 0 };
processor processor
.registers .registers
.set_flag_bit(register::Flag::Carry, full_carry_bit); .set_flag_bit(register::Flag::Carry, carry.into());
} }

6
src/cpu/run/load16.rs
View File

@ -33,14 +33,12 @@ impl InstructionRunner<SixteenBitLoadInstruction> for SixteenBitLoadRunner {
let (new_sp, half_carry, carry) = current_sp.add_with_carry(offset); let (new_sp, half_carry, carry) = current_sp.add_with_carry(offset);
let half_carry_bit = if half_carry { 1 } else { 0 };
let carry_bit = if carry { 1 } else { 0 };
processor processor
.registers .registers
.set_flag_bit(register::Flag::Carry, carry_bit); .set_flag_bit(register::Flag::Carry, carry.into());
processor processor
.registers .registers
.set_flag_bit(register::Flag::HalfCarry, half_carry_bit); .set_flag_bit(register::Flag::HalfCarry, half_carry.into());
// Manual says we reset these here. // Manual says we reset these here.
processor processor