Rename 8 bit immediate load isntructions
parent
e2365aec7e
commit
1795d652fa
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@ -38,7 +38,7 @@ macro_rules! assert_ok {
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impl Processor {
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fn run(&mut self, instruction: &RunnableInstruction) {
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match instruction.instruction {
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Instruction::LDnnn { value, register } => {
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Instruction::LD8BitImmediateToRegister { value, register } => {
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self.registers.set_single_register(register, value);
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}
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@ -5,7 +5,7 @@ use super::register;
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// http://marc.rawer.de/Gameboy/Docs/GBCPUman.pdf
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pub enum Instruction {
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// 3.3.1.1
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LDnnn {
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LD8BitImmediateToRegister {
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value: u8,
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register: register::Single,
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},
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@ -15,26 +15,26 @@ impl OpcodeParser for Immediate8BitLoadParser {
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let opcode = parse::get_opcode_from_data(data)?;
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match opcode {
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0x3E => make_ldnn_data(register::Single::A, data),
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0x06 => make_ldnn_data(register::Single::B, data),
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0x0E => make_ldnn_data(register::Single::C, data),
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0x16 => make_ldnn_data(register::Single::D, data),
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0x1E => make_ldnn_data(register::Single::E, data),
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0x26 => make_ldnn_data(register::Single::H, data),
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0x2E => make_ldnn_data(register::Single::L, data),
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0x3E => make_load_immediate_data(register::Single::A, data),
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0x06 => make_load_immediate_data(register::Single::B, data),
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0x0E => make_load_immediate_data(register::Single::C, data),
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0x16 => make_load_immediate_data(register::Single::D, data),
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0x1E => make_load_immediate_data(register::Single::E, data),
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0x26 => make_load_immediate_data(register::Single::H, data),
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0x2E => make_load_immediate_data(register::Single::L, data),
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_ => Err(Error::UnknownOpcode(opcode)),
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}
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}
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}
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fn make_ldnn_data(register: register::Single, data: &[u8]) -> ParseResult {
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fn make_load_immediate_data(register: register::Single, data: &[u8]) -> ParseResult {
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let opcode = parse::get_opcode_from_data(data)?;
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let value = data.get(1).ok_or(Error::NotEnoughArgs(opcode))?;
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Ok((
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RunnableInstruction {
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instruction: Instruction::LDnnn {
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instruction: Instruction::LD8BitImmediateToRegister {
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register,
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value: *value,
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},
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