 Nick Krichevsky
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733c18614c
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Add support for adding immediate to A register
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2022-04-23 22:31:22 -04:00 |
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Nick Krichevsky
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f97fbdcf9e
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Add rustdocs to arithutil
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2022-04-23 16:43:30 -04:00 |
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Nick Krichevsky
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e6b25cd54b
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Add overload to carry-add negatives
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2022-04-23 16:37:50 -04:00 |
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Nick Krichevsky
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418a659e07
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Simplify half carry checking logic
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2022-04-23 13:33:59 -04:00 |
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Nick Krichevsky
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dcf13061c6
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Add CarryingAdd trait and integrate it in existing addition locations
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2022-04-23 13:12:18 -04:00 |
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Nick Krichevsky
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807249ba18
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Use proper Error type when running instructions instead of panicking immediately
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2022-04-17 20:41:22 -04:00 |
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Nick Krichevsky
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16385f6387
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Break out instruction running code into its own module
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2022-04-16 10:59:07 -04:00 |
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Nick Krichevsky
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54cb2b8b2c
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Add (messy) implementation of adding 8 bit registers to others
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2022-04-14 23:28:29 -04:00 |
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Nick Krichevsky
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29ccffccf7
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Replace 'ld' with Load
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2022-04-14 21:30:49 -04:00 |
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Nick Krichevsky
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deeacd917a
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Simplify register access code
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2022-04-14 21:22:05 -04:00 |
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Nick Krichevsky
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f1e72b45de
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Restructure instruction enums to be categorized based on the type of instruction
This helps break up some of the long match statement in Processor::run, but construction does become a bit annoying.
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2022-04-11 23:52:44 -04:00 |
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Nick Krichevsky
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16bc8833d5
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Remove unused 'use'
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2022-04-11 23:10:26 -04:00 |
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Nick Krichevsky
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84e680fd15
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Implement stack push and pop
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2022-04-11 23:10:26 -04:00 |
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Nick Krichevsky
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cfebc1b912
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Implement (messy) LEA for stack pointer addresses
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2022-04-09 18:34:11 -04:00 |
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Nick Krichevsky
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a7adfb6f90
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Implement transfers between HL and SP
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2022-04-09 15:43:28 -04:00 |
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Nick Krichevsky
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0667a59c6a
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Fix incorrect opcode for loading load then inc, add variant for loading from memory
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2022-04-09 14:43:53 -04:00 |
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Nick Krichevsky
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30e45bee72
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Clean up load8::transfer
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2022-04-09 14:02:59 -04:00 |
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Nick Krichevsky
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034811c54e
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Implement loading to the stack pointer
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2022-04-09 14:00:33 -04:00 |
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Nick Krichevsky
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d85c7b8a98
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Add support for programatically manipulating 16 bit registers
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2022-04-09 13:57:50 -04:00 |
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Nick Krichevsky
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ef2aff5a8e
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Rename Single to SingleEightBit
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2022-04-09 13:47:26 -04:00 |
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Nick Krichevsky
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3803abfa1d
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Add support for loading 16 bit immediate values to combined registers
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2022-04-09 13:35:17 -04:00 |
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Nick Krichevsky
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1795d652fa
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Rename 8 bit immediate load isntructions
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2022-04-09 13:09:27 -04:00 |
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Nick Krichevsky
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e2365aec7e
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Add ability to load from i/o registers relative to immediate
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2022-04-08 21:10:47 -04:00 |
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Nick Krichevsky
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75235ad5e0
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Refactor run.rs to reduce repetition and use proper Error types
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2022-04-08 19:42:37 -04:00 |
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Nick Krichevsky
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af38d1edf4
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Implement load + inc/dec opcodes
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2022-04-08 18:50:26 -04:00 |
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Nick Krichevsky
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9a7f1ed093
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Add ability to read/write to i/o register zone
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2022-04-08 17:46:54 -04:00 |
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Nick Krichevsky
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769e4bc2ab
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Replace panic checks with unwrap_or_else in Processor
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2022-04-08 17:14:19 -04:00 |
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Nick Krichevsky
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ac541822db
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Add Display on register traits
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2022-04-08 16:38:46 -04:00 |
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Nick Krichevsky
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4e6e3f7680
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Add TODO about cycles
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2022-04-07 18:13:49 -04:00 |
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Nick Krichevsky
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d419500279
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minor style fix
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2022-04-07 00:33:04 -04:00 |
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Nick Krichevsky
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a7761215b5
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Remove unneeded macro in transfer module
This is a lot more readable now that we can squeeze it onto one line
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2022-04-07 00:32:44 -04:00 |
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Nick Krichevsky
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066189708b
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Move static methods for RunnableInstruction into parse package
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2022-04-07 00:29:39 -04:00 |
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Nick Krichevsky
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0c53bd2c6b
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Break up memory parsing module
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2022-04-06 23:06:03 -04:00 |
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Nick Krichevsky
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ad62658980
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Rustdocs
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2022-04-06 22:47:38 -04:00 |
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Nick Krichevsky
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8734a7fc8e
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Make a macro for the transfer module
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2022-04-06 22:43:38 -04:00 |
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Nick Krichevsky
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e5609972c8
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Move instruction parsing into its own module
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2022-04-06 21:01:11 -04:00 |
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Nick Krichevsky
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6d4ffc03ef
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Implement loading to/from A register and fix loading from immediate address
Was pulling from the wrong data in the stream to get the address, and
the test basically was a nop
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2022-04-05 22:13:39 -04:00 |
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Nick Krichevsky
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c491b180fc
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Fix clippy lint
We kinda have to allow this to be this long, lest we ant this method to
devolve into macro hell
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2022-04-05 00:24:25 -04:00 |
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Nick Krichevsky
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28132d60fa
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Add support for loading to A from immediate address
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2022-04-05 00:22:20 -04:00 |
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Nick Krichevsky
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cb535e24c3
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Add loading of addresses in other combined registers than (hl)
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2022-04-05 00:19:19 -04:00 |
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Nick Krichevsky
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e95cd263c5
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Implement load immediate to (hl)
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2022-04-04 23:41:25 -04:00 |
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Nick Krichevsky
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dcaf0588de
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Add load to (hl) instructions
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2022-04-04 23:34:34 -04:00 |
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Nick Krichevsky
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1dc176fd74
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Add load from (hl) instructions
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2022-04-04 23:12:59 -04:00 |
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Nick Krichevsky
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4c6eec264a
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Add basic memory for load instruction backing
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2022-04-04 22:51:56 -04:00 |
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Nick Krichevsky
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af95676b15
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Add parsing of ldr1r2 instructions
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2022-04-04 22:18:15 -04:00 |
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Nick Krichevsky
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92b779d02d
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Add parsing of ldnn instructions
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2022-04-02 11:01:04 -04:00 |
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Nick Krichevsky
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ac6097794d
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Add support for combined registers
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2022-04-01 19:48:13 -04:00 |
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Nick Krichevsky
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607e4ab2df
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Add flag register setting
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2022-04-01 19:21:33 -04:00 |
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Nick Krichevsky
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fc710000a4
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Initial commit. Add registers
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2022-04-01 18:11:09 -04:00 |