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jsmoo

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old-bit-manip

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• f0c0e818c9 Implement add A to HL instruction Nick Krichevsky 2022-04-23 23:46:44 -0400
• 733c18614c Add support for adding immediate to A register Nick Krichevsky 2022-04-23 22:31:22 -0400
• f97fbdcf9e Add rustdocs to arithutil Nick Krichevsky 2022-04-23 16:43:30 -0400
• e6b25cd54b Add overload to carry-add negatives Nick Krichevsky 2022-04-23 16:37:50 -0400
• 418a659e07 Simplify half carry checking logic Nick Krichevsky 2022-04-23 13:33:59 -0400
• dcf13061c6 Add CarryingAdd trait and integrate it in existing addition locations Nick Krichevsky 2022-04-23 13:12:13 -0400
• 807249ba18 Use proper Error type when running instructions instead of panicking immediately Nick Krichevsky 2022-04-17 19:28:11 -0400
• 16385f6387 Break out instruction running code into its own module Nick Krichevsky 2022-04-16 10:59:07 -0400
• 54cb2b8b2c Add (messy) implementation of adding 8 bit registers to others Nick Krichevsky 2022-04-14 23:25:46 -0400
• 29ccffccf7 Replace 'ld' with Load Nick Krichevsky 2022-04-14 21:30:49 -0400
• deeacd917a Simplify register access code Nick Krichevsky 2022-04-14 21:22:05 -0400
• f1e72b45de Restructure instruction enums to be categorized based on the type of instruction Nick Krichevsky 2022-04-11 23:52:44 -0400
• 16bc8833d5 Remove unused 'use' Nick Krichevsky 2022-04-11 23:09:11 -0400
• 84e680fd15 Implement stack push and pop Nick Krichevsky 2022-04-11 22:54:55 -0400
• cfebc1b912 Implement (messy) LEA for stack pointer addresses Nick Krichevsky 2022-04-09 18:25:41 -0400
• a7adfb6f90 Implement transfers between HL and SP Nick Krichevsky 2022-04-09 15:11:03 -0400
• 0667a59c6a Fix incorrect opcode for loading load then inc, add variant for loading from memory Nick Krichevsky 2022-04-09 14:41:50 -0400
• 30e45bee72 Clean up load8::transfer Nick Krichevsky 2022-04-09 14:02:59 -0400
• 034811c54e Implement loading to the stack pointer Nick Krichevsky 2022-04-09 14:00:33 -0400
• d85c7b8a98 Add support for programatically manipulating 16 bit registers Nick Krichevsky 2022-04-09 13:57:50 -0400
• ef2aff5a8e Rename Single to SingleEightBit Nick Krichevsky 2022-04-09 13:32:12 -0400
• 3803abfa1d Add support for loading 16 bit immediate values to combined registers Nick Krichevsky 2022-04-09 13:30:00 -0400
• 1795d652fa Rename 8 bit immediate load isntructions Nick Krichevsky 2022-04-09 13:09:27 -0400
• e2365aec7e Add ability to load from i/o registers relative to immediate Nick Krichevsky 2022-04-08 21:10:47 -0400
• 75235ad5e0 Refactor run.rs to reduce repetition and use proper Error types Nick Krichevsky 2022-04-08 19:42:37 -0400
• af38d1edf4 Implement load + inc/dec opcodes Nick Krichevsky 2022-04-08 18:49:53 -0400
• 9a7f1ed093 Add ability to read/write to i/o register zone Nick Krichevsky 2022-04-08 17:46:54 -0400
• 769e4bc2ab Replace panic checks with unwrap_or_else in Processor Nick Krichevsky 2022-04-08 17:00:44 -0400
• ac541822db Add Display on register traits Nick Krichevsky 2022-04-08 16:38:46 -0400
• 4e6e3f7680 Add TODO about cycles Nick Krichevsky 2022-04-07 18:13:35 -0400
• d419500279 minor style fix Nick Krichevsky 2022-04-07 00:33:04 -0400
• a7761215b5 Remove unneeded macro in transfer module Nick Krichevsky 2022-04-07 00:32:44 -0400
• 066189708b Move static methods for RunnableInstruction into parse package Nick Krichevsky 2022-04-07 00:29:39 -0400
• 0c53bd2c6b Break up memory parsing module Nick Krichevsky 2022-04-06 23:06:03 -0400
• ad62658980 Rustdocs Nick Krichevsky 2022-04-06 22:47:38 -0400
• 8734a7fc8e Make a macro for the transfer module Nick Krichevsky 2022-04-06 22:43:38 -0400
• e5609972c8 Move instruction parsing into its own module Nick Krichevsky 2022-04-06 21:01:11 -0400
• 6d4ffc03ef Implement loading to/from A register and fix loading from immediate address Nick Krichevsky 2022-04-05 22:13:33 -0400
• c491b180fc Fix clippy lint Nick Krichevsky 2022-04-05 00:24:20 -0400
• 28132d60fa Add support for loading to A from immediate address Nick Krichevsky 2022-04-05 00:21:58 -0400
• cb535e24c3 Add loading of addresses in other combined registers than (hl) Nick Krichevsky 2022-04-05 00:02:09 -0400
• e95cd263c5 Implement load immediate to (hl) Nick Krichevsky 2022-04-04 23:41:25 -0400
• dcaf0588de Add load to (hl) instructions Nick Krichevsky 2022-04-04 23:34:34 -0400
• 1dc176fd74 Add load from (hl) instructions Nick Krichevsky 2022-04-04 23:11:18 -0400
• 4c6eec264a Add basic memory for load instruction backing Nick Krichevsky 2022-04-04 22:51:56 -0400
• af95676b15 Add parsing of ldr1r2 instructions Nick Krichevsky 2022-04-04 22:18:15 -0400
• 92b779d02d Add parsing of ldnn instructions Nick Krichevsky 2022-04-02 11:01:04 -0400
• ac6097794d Add support for combined registers Nick Krichevsky 2022-04-01 19:47:41 -0400
• 607e4ab2df Add flag register setting Nick Krichevsky 2022-04-01 19:06:36 -0400
• fc710000a4 Initial commit. Add registers Nick Krichevsky 2022-04-01 18:10:56 -0400